The complication of adulterated ingredients in processed food items is widely observed in the food industry and remains a continuous disquiet for end users. This problem may affect consumers' spiritual beliefs, likewise with their fitness and diet. Hence commercial foods should be scrutinized for the precision of the avowed ingredients. This study is dedicated to developing a Fluorescent light Spectroscope to identify the pork adulteration. A simple way of DNA extraction process has been introduced to make the system more convenient. The spectral bands linked with pork fat (PF), beef fat (BF) and their combinations in different food formulation were skimmed, and recognized by correlating them to those spectroscopically illustrative to clean Pork or PF and other different items. Every material has the properties to absorb some light of specific wavelength, and our activity is to determine thus wavelength range at which are absorbed or make any change by the target material. The findings have revealed that spectroscopy can be used as one of the procedures to detect and quantify of pork in different foods and beverages formulation for Halal verification purposes. Special laborious procedures and equipment both are essential for the existing testing methods named RT-PCR (Reverse transcription-polymerase chain reaction) and ELISA (enzyme-linked immunosorbent assay). Most of the food processors and dealers are not skillful to conduct sufficient testing for their products with all these sample preparation, extraction, analysis, and obtaining results which can be overcome by our proposed setup.

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Abstract:Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.

Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.