Sapphire (alpha-Al2O3) is an important ceramic material that is widely used in substrate material for electronics. We investigate the chemical reaction layer on a sapphire wafer using X-ray photoelectron microscopy (XPS) and atomic force microscopy (AFM). The frictional characteristics of sapphire chemical mechanical polishing (CMP) was studied using in-situ friction force monitoring system. From XPS analysis and AFM experiment, a chemically-reacted layer was verified on the sapphire surface through a chemical reaction between the sapphire and chemicals in a slurry. During sapphire CMP, the friction force mainly depended on the applied pressure. The material removal efficiency per unit friction energy in sapphire CMP was 6.18 nm/kJ.

Chemical mechanical polishing (CMP) is a process with relative motion between pad and wafer while supplying slurry which abrasive particles are dispersed. This process consists of mechanical action by contact between pad and wafer and chemical action by the slurry chemicals. There are various factors affecting on material removal rate (MRR) in CMP. Especially, the pad plays a role of mechanical action by direct contact with wafer. Real contact area (RCA) between pad and wafer is an important factor when considering real contact pressure, friction and wear of pad asperities, which affects on the MRR and within wafer non-uniformity (WIWNU). This paper proposes a correlation between pad property and MRR in CMP process. The pad after conditioning had sharp asperities and changed to blunt ones as the polishing time became longer. This phenomenon was clarified by the roughness parameter of R ku . The high R ku pad just after conditioning made a high real pressure to the wafer, resulting in high MRR during CMP.

This paper deals with the planarization of copper bumps to improve the bonding performance and reliability of printed circuit board (PCB) manufacturing to improve by using flip chip during the fabrication process of the PCB. Authors tried to develop a novel planarization process using polishing techniques before the continuous process at the PCB fabrication. An experiment was implemented by mechanical polishing (MP) using alumina abrasives mixed with deionizer water (DIW), and by chemical mechanical polishing (CMP) added with oxidizer of HF. CMP showed superior results to MP with mirror surface less than Ra 3nm and minimum step height deviation of 1um, resulting in high bonding performance and reliability. Therefore, CMP is a strong tool for reserving a sufficient margin in the PCB manufacture process.

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Through silicon via (TSV) technology is becoming a mainstream method of building 3-dimensional integrated circuits (3D IC). In particular, TSV Cu CMP is a critical process to remove excess Cu and makes a planar surface which requires a removal rate higher than 5 microm/min and a dishing lower than 0.3 microm. This paper focuses on the development of a new self-alignment method using dimples on the TSV Cu back surface. We tried to find an application potential of a bump-dimple structure for self alignment using a pretest tool of a solder ball array structure. Chemical-mechanical planarization (CMP) aided dimple etching is carefully studied as a key solution for deep and uniform dimple formation. The experiment shows that CMP is an excellent process to generate a clean oxide surface and a clear dishing on the Cu TSV, resulting in a seed for etching. Finally, etching realizes a uniform dimple depth of 7 microm to 9 microm in spite of changes of via diameter from 10 microm to 50 microm after only 15 sec etching.