This investigation explores piezoelectricity generation from ZnO nanorods, which were grown on silver coated textile cotton fabrics using the low temperature aqueous chemical growth method. The morphology and crystal structure studies were carried out by x-ray diffraction, scanning electron microscopic and high resolution transmission electron microscopic techniques, respectively. ZnO nanorods were highly dense, well aligned, uniform in spatial distribution and exhibited good crystal quality. The generation of piezoelectricity from fabricated ZnO nanorods grown on textile cotton fabrics was measured using contact mode atomic force microscopy. The average output voltage generated from ZnO nanorods was measured to be around 9.5 mV. This investigation is an important achievement regarding the piezoelectricity generation on textile cotton fabric substrate. The fabrication of this device provides an alternative approach for a flexible substrate to develop devices for energy harvesting and optoelectronic technology on textiles.

In the present work, NiCo2O4 nanostructures are fabricated in three dimensions (3D) on nickel foam by the hydrothermal method. The nanomaterial was characterized by scanning electron microscopy (SEM), X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS). The nanostructures exhibit nanoneedle-like morphology grown in 3D with good crystalline quality. The nanomaterial is composed of nickel, cobalt and oxygen atoms. By using the favorable porosity of the nanomaterial and the substrate itself, a sensitive glucose sensor is proposed by immobilizing glucose oxidase. The presented glucose sensor has shown linear response over a wide range of glucose concentrations from 0.005 mM to 15 mM with a sensitivity of 91.34 mV/decade and a fast response time of less than 10 s. The NiCo2O4 nanostructures-based glucose sensor has shown excellent reproducibility, repeatability and stability. The sensor showed negligible response to the normal concentrations of common interferents with glucose sensing, including uric acid, dopamine and ascorbic acid. All these favorable advantages of the fabricated glucose sensor suggest that it may have high potential for the determination of glucose in biological samples, food and other related areas.

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel V t of ~±0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack.

In this work, a copper/zinc-oxide (ZnO)-nanorods-based Schottky diode was fabricated on the textile fabric substrate. ZnO nanorods were grown on a silver-coated textile fabric substrate by using the hydrothermal route. Scanning electron microscopy and x-ray diffraction techniques were used for the structural study. The electrical characterization of copper/ZnO-nanorodsbased Schottky diodes was investigated by using a semiconductor parameter analyzer and an impedance spectrometer. The current density-voltage (J-V) and capacitance-voltage (C-V) measurements were used to estimate the electrical parameters. The threshold voltage (V th ), ideality factor (η), barrier height (φ b ), reverse saturation current density (J s ), carrier concentration (N D ) and built-in potential (V bi ) were determined by using experimental data and (simulated) curve fitting. This study describes the possible fabrication of electronic and optoelectronic devices on textile fabric substrate with an acceptable performance.

Using strained SiGe on Si, the threshold voltage of high PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2 O 3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high and metal gates for 32nm node and beyond. Introduction While excellent advances have been made in acheving low NMOS threshold voltage with high performance [1-3], a manufacturable low PMOS V T still remains a challenge. We demonstrate here the modulation of PMOS V T with substrate band gap rather than relying on metal work function alone. The device is then integrated into the PMOS region with La 2 O 3 capping in the NMOS region to attain symmetric CMOS devices on the same chip, both with high performance. DiscussionThe issues with achieving proper valence band-edge work function for high /metal gate stacks have been well chronicled. [4,5] In examining the threshold voltage equation,The term V FB is composed of the several charge terms and the metal-semiconductor work function difference, MS = Metal -semi . In reducing V Tp , researchers have searched for a metal with high Metal to maximize MS and offset the other terms in V Tp .[6] However, an alternate approach is to minimize semi . This can be done by incorporating Ge into the channel which is known to move the valence band toward the vacuum level. [7] A comparison of the 1µm I D -V G curves for >10% SiGe channel and control Si in Fig. 1 indicates there is a shift of ~300mV and that the drive current for the SiGe device is significantly higher than the Si. This phenomenon is seen for several metals that are within ¼E g of the valence band edge (Fig. 2). The lower threshold voltage is attributed to two mechanisms: the change in band gap due to Ge in the SiGe [7] with a minor contribution from compressive strain of epitaxial SiGe directly on Si. [8] This is shown pictorially in Fig. 3 where a metal with work function of ~4.9 eV [9] is lined up with the valence band of the epitaxial SiGe. In Fig. 4, the gate leakage and C-V of ALD HfSiO directly on SiGe display excellent properties with EOT= 1.25nm and J G = 9.2A/cm 2 .Since a SiGe channel can provide the right PMOS threshold voltage, it is of interest to combine it with known NMOS solutions and demonstrate high performance. The integration scheme for combining these elements on the same wafer is outlined in Fig. 5. [10] Afer the NMOS gate stack is deposited and masked off, the PMOS Si is slightly recessed and selective epitaxy of >10% SiGe is grown. The PMOS gate stack is then deposited and masked. After removal of the PMOS gate from the top of the NMOS mask, the hard masks are then removed and the poly is deposited. After this point standard planar CMOS processing is followed with 1070 o C activation anneal.Cross section TEMs of the PMOS devices at ~80nm and the gate stack HRTEM are seen in Fig. 6. The detai...