Graphene can be grown on three major low-index substrates of Si(111), (110), and (001) by forming a 3C-SiC thin film and by subliming Si atoms from the top few layers of the SiC film. We have investigated the structure of graphene/3C-SiC interface by cross-sectional transmission electron microscopy (XTEM) and Raman-scattering spectroscopy. While the interface layer quite similar to that on the graphene/6H-SiC(0001) face is found to exist on the 3C-SiC(111)/Si(111) substrate, no such interface structure exists on the (110)- and (001)-oriented faces.

Charge trapping and tunneling characteristics of silicon-nitride (Si3N4) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory (NVM). A critical thickness of Si3N4 layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress method. As a result, the optimization of Si3N4 thickness considerably improved the performances of NVM.

3C-SiC is the only polytype that grows heteroepitaxially on Si substrates and, therefore, it is of high interest for various potentail applications. However, the large (~20 %) lattice mismatch of SiC with the Si substrate causes a serious problem. In this respect, rotated epitaxy of 3C-SiC(111) on the Si(110) substrate is highly promising because it allows reduction of the lattice mismatch down to a few percent. We have systematically searched the growth conditions for the onset of this rotated epitaxy, and have found that the rotaed epitaxy occurrs at higher growth temperatures and at lower source-gas pressures. This result indicates that the rotated epitaxy occurs under growth conditions that are close to the equilibrium and is thefore thermodynamically, rather than kinetically, driven.

Charge trapping characteristics of asymmetrical tunnel barriers consisting of different dielectric materials were investigated for application of nonvolatile memory devices. A thin HfO 2 layer stacked on ultrathin SiO 2 layer (SiO 2 /HfO 2 tunnel barrier) revealed higher current sensitivity to applied gate voltage than the conventional single SiO 2 tunnel barrier. On the other hand, the electron trapping of the tunnel barriers increased with the thickness of HfO 2 layer. Thus, a thin HfO 2 layer is promising for the engineered tunnel barriers, while a thick HfO 2 layer is appropriate for charge trapping layers for high-integrated nonvolatile memories. Meanwhile, an ultrathin Al 2 O 3 /HfO 2 tunnel barrier also revealed good electrical characteristics and is suitable for low temperature fabrication process.