Minimizing the low-quality interfacial layer (IL) growth during high-k film deposition on III-V compound substrates has been a major research area, in addition to the development of various interface passivation techniques [1]. On GaAs substrates, Hinkle et al. [2] reported a pioneering work on the metal-organic (MO) precursoractivated self-cleaning effect, a spontaneous clean-up of the surface oxides during the atomic layer deposition (ALD) of HfO 2 and Al 2 O 3 . A similar cleaning effect was also observed on InGaAs [3,4]. Among many contributing parameters, the ALD temperature is known to strongly affect the self-cleaning mechanism; for example, Suri et al.[5] reported that it is insignificant at 200 °C and remarkably enhanced at 300 °C when tetrakis(dimethylamino)hafnium/H 2 O were used for HfO 2 deposition on GaAs. In conjunction with affecting the defective IL removal efficiency, the ALD temperature is also one of the important criteria in determining the final microstructural and electrical properties of the high-k films.Together with GaAs and InGaAs, InP is also a promising candidate as an alternative n-channel material, however, fewer works have been reported on the self-cleaning effect during the ALD high-k process on InP. Recently, an interesting IL evolution behavior showing a large dependence on the HfO 2 thickness was reported when tetrakis-(ethylmethylamino)hafnium (TEMAHf) and H 2 O were used on InP at an ALD temperature equal to or higher than 300 °C [6,7]. In these reports, largely insufficient selfcleaning was observed at an early stage and a continuous decrease of the IL occurred as the film thickness was increased, which is a quite different trend to that on GaAs or InGaAs, which shows a nearly complete removal of IL after only a few ALD cycles [2,4,5]. However, a detailed mechanism for this phenomenon was not given.On these grounds, we investigated the effect of the ALD temperature on the IL evolution during the HfO 2 formation on InP and tried to rationalize it by focusing on the temperature-dependent self-cleaning effect and possible simultaneous substrate oxidation during the ALD process. In addition, the film-thickness-dependent IL thickness variation was accounted for by other possible contributing factors.As substrates, (100)-oriented InP wafers with an n-type carrier concentration of (4−5) × 10 15 cm -3 were used. The substrates were successively cleaned by 1% HF and 21% (NH 4 ) 2 S diluted solutions. The ALD HfO 2 process was carried out in a cross-flow type ALD system at various substrate temperatures: 200, 250, and 300 °C. During each deposition cycle, TEMAHf and H 2 O were sequentially delivered with N 2 purging in between, and the total number The effects of both the deposition temperature and the HfO 2 film thickness on the interfacial layer (IL) evolution were studied when tetrakis(ethylmethylamino)hafnium and H 2 O based atomic layer deposition (ALD) was performed on InP substrates. While the self-cleaning effect resulted in an IL-free structure after formation of ~2 nm thick ...

In this study, we synthesized ZnO nanowires using Au catalytic particles formed on a ZnO seed layer. We modulated the microstructure of the ZnO seed layer by changing the sputtering power to investigate how the underlying ZnO film microstructure affects the distribution of ZnO nanowires. Examining the samples after each of the three key steps of the growth process (ZnO seed layer deposition, Au catalytic particle formation, and nanowire growth) using various characterization methods such as scanning electron microscopy, transmission electron microscopy, and x-ray diffraction helped us illuminate the profound impacts of the grain size of the seed layer on the nanowire density.

The effect of the deposition temperature (200, 250, and 300 8C) on the electrical properties of the atomic-layer-deposited [atomic layer deposition (ALD)] HfO 2 films on InP was studied. A significant grain growth as well as an increase in the accumulation capacitance occurred by increasing the ALD temperature from 200 to 250 8C. However, a further increase to 300 8C degraded the electrical properties as verified by various electrical characterizations, including an accumulation capacitance lowering, a near-interface defect (trap) formation, and an increase in the electrical stress-induced new trap generation, due to a significant In out-diffusion to the HfO 2 film side.

SiO 2 /Si 3 N 4 /SiO 2 tunnel barriers with a residual Si 3 N 4 layer of different thicknesses were fabricated by thermally oxidizing Si 3 N 4 /SiO 2 film. According to leakage current measurements, the effective barrier height was significantly lowered because the Si 3 N 4 middle layer has a lower bandgap than SiO 2 , which is beneficial in increasing the erasing/programming speed in flash memory devices. However, detrimental effects, such as the increased hysteresis in capacitance-voltage characteristics and the degraded breakdown distribution, were observed due to the significant amount of the charge trapping induced by the increased Si 3 N 4 thickness. For the sample with a distinctive Si 3 N 4 layer, trap-assisted tunneling and Fowler-Nordheim tunneling were the dominant conduction mechanisms at low and high electric field, respectively. However, the accumulation of N at the SiO 2 /Si interface for the fully oxidized sample resulted in an asymmetric conduction mechanism behavior, which was explained by the band diagram analysis.

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