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IntroductionFinFET-based multi-gate (MuGFET) devices are one of the most promising candidates for sub-32nm nodes. However, their viability for multiple-V T CMOS applications remains a challenge, since due to full depletion of the FINs, V T tuning options for narrow FINs are limited to workfunction (WF) tuning with metal gate (MG). Recent developments have shown that introducing a cap layer (La 2 O 3 [1], Dy 2 O 3 [2] for nmos; AlO x [3,4] for pmos) between a high-k host dielectric and MG can successfully tune its WF towards bandedge. This capping technology is also attractive for MuGFETs due to its compatibility with their 3-D architecture and suitability for use in high density circuits. In our previous work [5], we proposed a practical MuGFET CMOS integration scheme ( Fig.1) enabling multiple-V T s on the same wafer, with cap layers selectively inserted in the flow at different locations in the gate stack: HfSiO/TiN, HfSiO/cap/TiN or HfSiO/TiN/cap/TiN (cap=Al 2 O 3 for pmos; Dy 2 O 3 or La 2 O 3 for nmos). In this paper, we investigate further the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1 st metal layer MG. Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence on the metal growth method (o metal density) than on its composition; b) studying the BTI behavior through a careful monitoring of the 'V transients. T Device fabricationMuGFET devices with 65nm Si (H FIN ) on 145nm BOX and W FIN t20nm were fabricated from a baseline CMOS flow described in [5,6] on SOI wafers. Reference gate stacks consist of 100nm a-Si + 5nm plasma enhanced-ALD (PE-ALD) TiN or AVD TaN deposited on 2.3nm MOCVD HfSiO with a 1nm interfacial oxide layer. Thin (d1nm) Dy 2 O 3 (by AVD) cap layers were inserted in nmos gate stacks immediately after HfSiO or in-between 2 metal layers depositions such that the total TiN (or TaN+TiN) thickness is 5nm. A dry-wet-dry gate patterning process was used for stacks with Dy 2 O 3 sandwiched in-between metal layers, allowing a selective cap wet removal. SEG (a750qC, 20-30min) was used prior to HDD I/I, followed by 1050qC spike anneal in N 2 .Results and discussion An overview of WF tuning results obtained in MuGFETs using capping technology and PE-ALD TiN [5] is shown in Fig.2, with 'WF data from varying the TiN gate electrode thickness also included. Next, an evaluation of the impact on device characteristics of varying the TiN thickness (Fig.3) and its deposition procedure (Fig.4) was done to be able to more accurately identify the cap contribution to the final device properties in MG/cap/MG deposited stacks, and to provide a 1 st assessment on possible integration issues. The results in Figs.3 and 4 show that while thinning down the TiN translates into CET decrease and WF shift (more n-type) (e.g., 'CET|2Å, 'V T a-100-120mV occur for 5o2nm TiN), as ...

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