Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack

Witters, L.; Son, N.J.; Ferain, I.; San, Tamer; Singanamalla, R.; Kerner, C.; Collaert, N.; Meyer, K. De; Jurczak, M.

doi:10.1109/soi.2007.4357838

Cited by 7 publications

(3 citation statements)

References 2 publications

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“…Accordingly, we propose tilted implantation as a means by which to form S/Ds ( Figure 2 d). Tilted implantation has already been extensively studied in relation to the formation of S/D in the FinFETs [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 ]. However, several problems arose during the commercialization process related to the tilted angle of implantation.…”

Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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Section: Resultsmentioning

confidence: 99%

3D AND-Type Stacked Array for Neuromorphic Systems

et al. 2020

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“…Owing to the lack of a back-gate bias option in fully depleted FinFET devices, complicated WF engineering is required to achieve multiple V th solution for undopped FinFET [14], [16], [17]. Ion implantation into metal gatestack of TiN/HfO2 provides suitable VT for devices keeping channel undopped.…”

Section: Methodology For Vt-targeting Using Work Function Tuningmentioning

confidence: 99%

“…In nanoscale CMOS technologies, innovative process and design solutions will help to achieve optimum performance for SRAM [12]. In this process, one important parameter to achieve the desired performance is work function (WF) tuning of metal gate [14]- [17]. Hence we present a systematic way of device VT-targeting for SRAM architectures to yield SRAM in variability-prone 10-nm-technology era.…”

Section: Introductionmentioning

confidence: 99%

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology highdensity (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546 μm 2 with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048 μm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1σ rsnm margin to retain the same yield in 10-nm-technology era.Index Terms-10-nm technology, design methodology, design technology co-optimization (DTCO), double patterning gate, FinFET SRAM design, high density (HD), selfaligned double patterning (SADP), self-aligned quadruple patterning (SAQP), SRAM threshold voltage (VT) targeting, technology SRAM.

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