For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.

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By applying flash lamp annealing (FLA) prior to spike RTA, we have successfully suppressed the dose loss and transient enhanced diffusion (TED) of indium for the first time. With steeper indium halo, a saturation drain current (I dsat) increase of 8% for 34 nm gate nMOSFET is demonstrated. Mechanisms of reduced dose loss are investigated by atomistic kinetic Monte Carlo (kMC) simulation. With FLA, initially created end-of-range (EOR) defects evolve into few and big {311} defects and even into loops. As a result, the interstitial supersaturation is suppressed by a factor of 1/100 which, in turn, reduces TED and dose loss of indium at following spike RTA. Furthermore, by combining carbon co-implantation with FLA, maximum indium concentration can be increased to 1×10 19 cm-3 .