The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8 × 8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance.

No abstract

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

High speed, low power, area efficient adders continue to play a key role in hardware implementations of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This paper proposes a unique custom adder design in 2S0-nm CMOS technology, which is based on a combination of CPL and CS logic to obtain a fast and power/area efficient adder design. A 16 bit CPLICS adder is presented which is faster compared to the standard SQRT CS adder while significantly reducing the power and area.

The continued quest for finding a low-power and high-performance hardware algorithm for signed number multiplication led to designing a simple and novel radix-8 signed number multiplier with 3-bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre-computation stage constitutes magnitude calculation and non-trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8 X 8, 16 X 16, 32 X 32, and 64 X 64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power-delay-product of synthesized and post-layout designs using 32 nm CMOS technology with 1.05 V supply voltage.