Low-Cost and High-Performance 8 × 8 Booth Multiplier

Boppana, Naga Venkata Vijaya Krishna; Kommareddy, Jeevani; Ren, Shiyan

doi:10.1007/s00034-019-01044-x

Cited by 22 publications

(15 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The designs in refs. [3] and [4] are implemented in 32 nm CMOS technology along with the proposed designs. Performance metrics, summarized in Table 4, for these three designs also account for the power, delay, and area of the input and output registers.…”

Section: Optimized Pp Grouping and Bec (Binary Excess-1 Code)-like St...mentioning

confidence: 99%

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

Boppana

Ren

2023

The Journal of Engineering

View full text Add to dashboard Cite

The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage.

show abstract

Section: Optimized Pp Grouping and Bec (Binary Excess-1 Code)-like St...mentioning

confidence: 99%

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

Boppana

Ren

2023

The Journal of Engineering

View full text Add to dashboard Cite

show abstract

“…From this analysis, it is observed that the final adder can be replaced by the proposed RCA. Similarly, we have analysed the third multiplier (Booth multiplier) structure of [35]. In this structure, the radix 4 Booth encoding scheme is used to reduce the number of partial product rows for delay minimisation.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…In this section, we have analysed the various multiplier structures to identify the approach of employability of the proposed BTA in these structures and to observe the performance improvement as well. For this purpose, three recent multiplier structures, namely array multiplier [34], Wallace multiplier [34] and Booth multiplier [35] are analysed. Firstly, we have analysed

M \times N

array multiplier of [34] in which N partial product rows are generated using AND gates, where M and N denote the bit width of multiplicand and multiplier terms, respectively.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…Similarly, as compared to the existing Wallace multiplier of [34], the proposed BTA‐based Wallace multiplier of [34] involves 8.69% less area, 8.7% less delay and 11.37% less energy. Compared to the Booth multiplier of [35], the proposed BTA‐based Booth multiplier of [35] offers a saving of 25.9% in area and 35.6% in energy with marginally higher delay.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…From the above analysis we have reached to the conclusion that the proposed BTA can suitably be applied in these multiplier structures, which can significantly improve their performance. Therefore, for the performance comparison, we have considered the array and Wallace multiplier structures of [34], Booth multiplier structure of [35] and developed these multiplier structures using the proposed BTA. All these multiplier designs are coded in VHDL for

M = 8

and

N = 8

, and synthesised in Synopsys Design Compiler using TSMC 65 nm CMOS Library.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

See 2 more Smart Citations

Area–delay and energy efficient multi‐operand binary tree adder

Patel

Singhal

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

show abstract

A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Ghasemi

Fathi

Mousazadeh

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThe proposed booth decoder/encoder unit is an ultrahigh‐speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 μm CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate‐level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30–200% comparing related works and also improves the delay of the multiplier 4–21%. The power consumption and the area of the structure are 477 μw and 20 × 18 μm2, respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

show abstract

Low-Cost and High-Performance 8 × 8 Booth Multiplier

Cited by 22 publications

References 11 publications

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

Area–delay and energy efficient multi‐operand binary tree adder

A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Contact Info

Product

Resources

About