This paper addresses post-routing capacitance extraction during performance-driven layout. We rst show h o w basic drivers in process technology planarization and minimum metal density requirements actually simplify the extraction problem; we do this by proposing and validating ve foundations" through detailed experiments with representative 0 : 18m process parameters and a 3-D eld solver. We then present a simple yet accurate 2 1 2-D extraction methodology directly based on the foundations. This methodology has been productized and is being shipped with the Cadence Silicon Ensemble 5.0 product. We conclude that the 2 1 2-D approach has su cient accuracy for current and near-term process generations.

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