Triceratops developed complex dental morphology, allowing it to become a dominant herbivore in the late Mesozoic era.

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Direct wafer bonding process is used in semiconductor manufacturing for heterogeneous integration of devices. When two silicon wafers are directly bonded together, the alignment along the bonded interface is critical to device performance and yield. This paper studies the relative alignment, or post-bond distortion, of a direct wafer bonding process using finite element simulation method. The methodology of constructing a 2D axisymmetric model to calibrate a 3D model is discussed. The simulation results showed that the post-bond distortion was sensitive to upper wafer pre-bond shapes and does not depend on lower wafer shapes. The simulation models enable reduced hardware development costs and time.

Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

As device sizes continue to shrink, accurate alignment in semiconductor wafer bonding process becomes more important. In the case of two patterned wafers directly bonded together, proper alignment of the electrical connections between the two bonding surfaces is critical. Misalignment between the wafers during bonding may lead to degraded electrical performance or even device failure. In the case of a patterned wafer directly bonded onto a blank carrier wafer, the relative displacement along the bonded interface is important for subsequent steps. This relative displacement contributes to overlay error in lithography steps. Furthermore, as device density continues to increase, pre-bond wafer shapes become more complex while warp magnitude increases. The distortion contribution from pre-bond wafer shapes becomes more significant as a result. Therefore, it is important to understand the direct wafer bonding distortion mechanics to reduce the yield impact of the process. This paper develops a mechanics model to study wafer bonder performance. An axisymmetric solid mechanics model simulates the wafer bonding dynamics by using a rate-dependent adhesion model. This simulation model includes calibration parameters to tune against experimental results. Using the optimized calibration parameters, an extended 3D simulation model studies more complex phenomena. This paper will report the simulation results that include local variations in wafer properties, clamping and thermal fluctuation effects. Distortion impact due to pre-bond wafer shapes, such as the relative contributions from the pre-bond wafer pair, is also discussed. The results of this model can enable improved hardware optimization to address stricter distortion requirements. This model can optimize key hardware features in lieu of large number of wafer tests to minimize the cost of development. Using this model, target performance can be achieved with fewer hardware iterations and reduce development time. Bonder recipes can also be designed and optimized to account for pre-bond wafer characteristics.