The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-ƙ dielectrics. The high-ƙ dielectric material in the place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (DG) MOSFET has been proposed. The capacitance modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the results derived from previous research and tabulated. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF hybrid applications.

Cylindrical Surrounding Double-Gate (CSDG) MOSFETs have been designed for a suitable CMOS replacement to diminish the power and area tradeoff. With these MOSFETs below 70 nm node for Semiconductor Industry Association (SIA) roadmap, the CMOS technology has excellent immunity to the Short Channel Effects (SCE) and better scalability. To reduce the SCE, the device was analyzed by improving the gate oxide thickness between the gate terminal and channel material and replacing the conventional Silicon dioxide layer with numerous high-ƙ dielectric materials. The gate oxide thickness is scalable so that it should have the same thickness as that of the Equivalent Oxide Thickness (EOT). This kind of novel structure shows improvement in the ON-state current and OFF-state current. The usage of the cylindrical surrounding double-gate and the high-ƙ dielectric in the oxide layer makes the MOSFET with improved stability and controllability. In this paper, the high-ƙ material is chosen in a way that it has been applied in the CSDG environment and the electrical field, electron densities have been analyzed. The semiconductor can exhibit various energy bands at the Fermi level, commonly referred to as valley. These kinds of valley semiconductors, which have several valleys are called multi-valley semiconductors. The current value in valley-1 is 2.41 mA/μm; it also drops to 62.14 % than valley-4, which has 6.38 mA/μm. However, valley-2 and valley-3 have intermediate values. The energy in the sub-band for the operating region of the source has been observed to be 19.12 % to the drain side which has the value of 0.041 eV at the terminal end. This shows the modeled CSDG MOSFET works well with the operating electric field created by the cylindrical capacitors constituted by the two different gate materials surrounding the substrate.

The structural improvement and rapid production of InP, InAs (III-V, binary), and AlGaAs (III-V, ternary) compound semiconductor materials have invariably enabled its utilization in typical highspeed device applications. Using the electronic simulator tool, the ON-and OFF-state drain current (ION/IOFF) performance of InP/InAs/AlGaAs High Electron Mobility Transistors (HEMTs) with Lanthanum Oxide (La2O3) as a dielectric material has been analyzed and thereafter a design of cylindrical surrounding gate MOSFET has been planned with this novel heterostructures. The InAs spacer (primary) layer is placed as per requirement below the source and drains the terminal to improve mobility. A heavily doped AlGaAs channel layer is employed beneath the primary layer, followed by the required layers. The given device gate length of LG = 5 nm, source-drain device length LSD = 0.15 μm and VGS = VDS = 1 V of InP/InAs/Al0.53Ga0.47As HEMT having Equivalent Oxide Thickness (EOT) of La2O3 as 2 nm (gate dielectric oxide), the measured values of maximum drain current (ID, max), transconductance (Gm), Charge carrier density (ρ), and leakage current (Ileak) are 10 mA/µm, 12 mS/µm, 1.5 C/cm 3, and 0.03 μA/μm respectively. The electrostatic potential (φ) and electric field (E) are 2.58 V and -47.12 V/μm are obtained when VDS= 1 V. This proposed design enhances the heterostructures immune to all the Short Channel Effects (SCEs) in the RF range that can be used in low power circuits design. Furthermore, the rotational cylindrical structure paves the way for a lesser board area to be occupied to reduce heat generation.

In this work, three-dimensional modeling of the surface potential along the cylindrical surrounding double-gate (CSDG) MOSFET is proposed. The derived surface potential is used to predict the values of electron mobility along the length of the device, thereby deriving the drain current equation at the end of the device. The expressions are used for modeling the symmetric doped and undoped channel CSDG MOSFET device. This model uses Pao-Sah’s double integral to derive the current equation for the concentric cylindrical structure of the CSDG MOSFET. The three-dimensional surface potential estimation is performed analytically for doped and undoped device parameters. The maximum oxidant concentration of the oxide layer is observed to be 4.37 × 1016 cm−3 of the thickness of 0.82 nm for (100) and 3.90 × 1016 cm−3 of the thickness of 0.96 nm for (111) for dry oxidation, and 2.56 × 1019 cm−3 of thickness 0.33 nm for (100) and 2.11 × 1019 cm−3 of thickness 0.49 nm for (111) for wet oxidation environment conditions. Being an extensive analytical approach, the drain current serves the purpose of electron concentration explicitly inside the concentric cylindrical structures. The behavior of the device is analyzed for various threshold conditions of the gate voltage and other parameters.

This research work uses sp3d5s* tight-binding models to design and analyze the structural properties of group IV and III-V oriented, rectangular Silicon (Si) and Gallium Arsenide (GaAs) Nanowires (NWs). The electrical characteristics of the NWs, which are shielded with Lanthanum Oxide (La2O3) material and the orientation with z [001] using the Non-Equilibrium Green Function (NEGF) method, have been analyzed. The electrical characteristics and the parameters for the multi-gate nanowires have been realized. A nanowire comprises a heavily doped n+ donor source and drains doping and n-donor doping at the channel. The specified nanowire has a gate length and channel length of 15 nm each, a source-drain device length LSD = 35 nm, with La2O3 as 1 nm (gate dielectric oxide) each on the top and bottom of the core material (Si/GaAs). The Gate-All-Around (GAA) Si NW is superior with a high (ION/IOFF ratio) of 1.06 × 109, and a low leakage current, or OFF current (IOFF), of 3.84 × 10−14 A. The measured values of the mid-channel conduction band energy (Ec) and charge carrier density (ρ) at VG = VD = 0.5 V are −0.309 eV and 6.24 × 1023 C/cm3, respectively. The nanowires with hydrostatic strain have been determined by electrostatic integrity and increased mobility, making them a leading solution for upcoming technological nodes. The transverse dimensions of the rectangular nanowires with similar energy levels are realized and comparisons between Si and GaAs NWs have been performed.