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The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.

This paper will present experimental details of a sorting module demonstration system. The sorting module which is currently under construction is shown as a functional schematic in figure 1. Figure 2 is a photograph of the optics. The system implements the bitonic sort based on Batcher’s algorithm implemented with a perfect shuffle. A re-circulating rather than pipelined arrangement is used to minimise hardware requirements to 2 smart pixel chips; • a sorting node array (self-routing exchange/bypass nodes), and • shift register array which acts as the input/output interface.

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