No abstract

In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.

No abstract

No abstract

A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mmlong interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 µm width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured eye diagrams allow us to compare the performance of the different test systems in combination with a fitted model. All considered systems show operation frequencies higher than 200 MHz for an eye height of at least 35 %. It is demonstrated that the communication system performance is mainly dominated due to weak driver strength (R S > 250 Ω) and secondly by the interconnection dimensions. Design considerations are proposed from the observed results.