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This is because the high conductivity of the poly-Si does not impede a transport limitation. Therefore, a separation of the n-type POLO (nPOLO) and p-type POLO (pPOLO) contact fingers is required [25][26][27][28][29] .In this work we employ a POLO junction scheme that consists of an initially full area intrinsic poly-Si (i poly-Si) layer that is locally doped by ion implantation. From process leanness point of view an attractive option to avoid these pn junctions in the poly-Si is to leave an (i) poly-Si region between emitter and base fingers. This is expected to result in lateral p(i)n poly-Si junction at the rear side of the IBC cell, which is connected in parallel to the nPOLO/p-type c-Si junctions ( Fig. 1a). By applying the described junction scheme we demonstrated a solar cell with an efficiency of 26.1% 11,21 .This concept was previously tested by other groups on precursor level 30 achieving a V OC of 682 mV with an pFF of 80% and on the cell level 27 yielding an efficiency of 18.4%. Both devices showed high ideality factors pointing to a non-ideal recombination in the space charge region. To evaluate why our cell, in contrast, does not suffer from a high ideality factor we perform a systematic study of the device physics of the resulting p(i)n poly-Si diodes.We quantify the defect density in our poly-Si layers prior and after hydrogenation using time-dependent photoluminescence decay measurements in the picosecond regime.As the purpose of the (i) poly-Si regions is to suppress high recombination currents across the p(i)n diode a large (i) poly-Si region is desirable. On the other hand, we observed a poor passivation quality of the c-Si absorber by the iPOLO on full-area lifetime test structures (see below). This is due to the moderate chemical passivation of SiO x on p-type Si, which further degrades when forming the nanometer-sized pinholes in the interfacial oxide 31 . This reasoning favors small (i) poly-Si widths. To find an optimum between these counteracting requirements, we experimentally vary the width of the (i) poly-Si region from nominal d gap = 0 µm up to 380 µm.We experimentally find that a width of the initially i poly-Si layer of d gap = 30 µm together with a high annealing temperature of over 1000 °C enables a record cell efficiency of 26.1%. From measurements on full area test structures and numerical device simulations we know that the surface recombination velocity at the intrinsic poly-Si is above 2000 cm/s and would limit the device efficiency to 15%. We conclude that the nominally intrinsic poly-Si layer is no longer intrinsic after the full cell process.We therefore investigate an inter-diffusion of dopants from the n-type and p-type doped fingers into the initially intrinsic poly-Si region by a lateral Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS) measurement. Combining all three aspects, we are, for the first time, able to present a comprehensive understanding of the working principle of high-efficient POLO IBC cells with p(i)n poly-Si diodes. Scientific RepoRtS |(202...

We present a semi-analytical model for the calculation of the current through and the recombination in carrier-selective junctions consisting of a poly-Si/SiO x /c-Si layer stack. We calculate the recombination parameter J 0 and the contact resistance ρ C after solving the band-bending-problem on both sides of the interfacial oxide. Comparisons with finite-element simulations show that the current calculation is reliable at all bias conditions except for inversion and that current through pinholes is resolved adequately in the model. The model allows a coherent description of lifetime-, current-voltage-and capacitance-voltage measurements performed on a sample with dominant tunneling. We use our model to investigate the influence of oxide thickness and pinhole density on J 0 and ρ C of our state-of-the-art poly-siliconon-oxide (POLO) junctions and demonstrate its usefulness for the optimization of poly-Si based junctions.

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