Nanotopography is the nanometer-scale height variation that occurs over lateral millimeter length scales on unpatterned silicon wafers [1][2]. This height variation can result in excess thinning of surface films during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures. The development of an accurate nanotopography CMP modeling and characterization procedure will allow for the proper diagnosis of potential problems due to wafer nanotopography in a given STI CMP process. In this work, a nanotopography modeling methodology is proposed which relates the length scale of nanotopography features to the length scale of the CMP process. A combined densityhtep-height polishing model indicates that when the nanotopography features occur over a range comparable to or shorter than the planarization length, appreciable thinning is predicted. A contact wear CMP model similarly shows that as the pad stiffness increases, film thinning also increases. These simulation results indicate that the effect of nanotopography on STI CMP may be a substantial concern.

Power spectral densities (PSDs) were used to characterize a set of surfaces over a wide range of lateral as well as perpendicular dimensions. Twelve 200-mm-diameter Si wafers were prepared and the surface finishes ranged from as-ground wafers to epitaxial wafers. The wafer surfaces were then measured with different methods: atomic force microscopy, angle-resolved light scatter, interferometric microscopy, optical profiling, stylus profiling, and capacitance-based wafer thickness gaging. The data were used to compute one-dimensional PSDs and the curves were plotted as functions of spatial frequencies, comparing results for different samples or for different instruments. The useful frequency range for each method is indicated and differences in the calculated PSD values in the overlapping region of two or more methods are discussed. The method used to convert two-dimensional PSDs to one-dimensional ones is presented.

As the demand for planarity increases with advanced IC technologies, nanotopography has arisen as an important concern in shallow trench isolation (STI) chemical mechanical polishing (CMP) processes. Previous work has shown that nanotopography, or small surface height variations on raw wafers 20 to 50 nm in amplitude extending across millimeter scale lateral distances, can result in substantial CMP-induced localized thinning of surface films such as oxides or nitrides used in STI [1]. This interaction with CMP depends both on characteristics of the wafer such as heights and spatial wavelengths of the nanotopography, and characteristics of the CMP process including the planarization length or pad stiffness.

Nanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems.Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested.In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data.

Detecting voids in bonded wafer pairs is critical for ensuring robust bonding processes and managing yield. Here, a new measurement technique to detect voids in bonded using scanning infrared (IR) interferometry is described and used to detect voids in direct-bonded silicon wafer pairs. The void measurements obtained with the scanning IR interferometry technique are compared to measurements made on the same wafers using IR transmission imaging and scanning acoustic microscopy.