This paper describes a 3D Integrated Circuit (3D-IC) architecture of a burst image sensor (BIS) with embedded digitization and digital storage. This architecture also proposes a new technique to further increase both the frame rate and the stored image capacity at the cost of a spatial resolution reduction. A 2D monolithic demonstrator that takes into account the constraints of a future 3D-IC imager has been fabricated. Experimental results are presented showing that a frame rate from 5 up to 45 Mega frames per second can be achieved. This fully functional approach paves the way to the very first in-focalplane digital BIS.

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Ultra-fast photon counting in standard CMOS imagers can become very challenging at sub-nanosecond temporal resolutions. This is due to the delay and skew of signal propagation along large pixel arrays. A new edge-based solution is presented, circumventing these limitations. This solution is applied to a Single Photon Avalanche Diode based pixel with an embedded analog counter for time gating photon counting. The analog counter has an adjustable sensitivity ranging from 0.1 mV/photon up to 100 mV/photon. This concept was applied to an image sensor with a row length of approximately 15 mm and 330 pixels per row. The pixel counts 55 transistors with a pitch of 45 µm.

A transmission line induced skew reduction system for shutter signals of a pixel array has been designed using TowerJazz CIS 0.18µm technology. It is based on the use of multiple delay-locked loop in charge of close-to-close synchronization. The simulation results demonstrate the ability of the system to compensate the transmission line induced skew from 1.58ns to 75ps. The measurements made with a prototype integrating a 11.6mm servo-controlled transmission line and fours delay-locked loop demonstrated a reduction of its skew down to 32ps.