No abstract

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adem.202101752.

Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermomechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapi d isothermal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed.In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry

No abstract

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.