As technology processes continue to shrink, standard design rule checking (DRC) has become insufficient to guarantee design manufacturability. DRCPlus is a powerful technique for capturing yield detractors related to complex 2D situations 1,2 . DRCPlus is a pattern-based 2D design rule check beyond traditional width and space DRC that can identify problematic 2D configurations which are difficult to manufacture. This paper describes a new approach for applying DRCPlus in a router, enabling an automated approach to detecting and fixing known lithography hotspots using an integrated fast 2D pattern matching engine. A simple pass/no-pass criterion associated with each pattern offers designers guidance on how to fix these problematic patterns. Since it does not rely on compute intensive simulations, DRCPlus can be applied on fairly large design blocks and enforced in conjunction with standard DRC in the early stages of the design flow. By embedding this capability into the router, 2D yield detractors can be identified and fixed by designers in a push-button manner without losing design connectivity. More robust designs can be achieved and the impact on parasitics can be easily assessed. This paper will describe a flow using a fast 2D pattern matching engine integrated into the router in order to enforce DRCPlus rules. An integrated approach allows for rapid identification of hotspot patterns and, more importantly, allows for rapid fixing and verification of these hotspots by a tool that understands design intent and constraints. The overall flow is illustrated in Figure 1. An inexact search pattern is passed to the integrated pattern matcher. The match locations are filtered by the router through application of a DRC constraint (typically a recommended rule). Matches that fail this constraint are automatically fixed by the router, with the modified regions incrementally re-checked to ensure no additional DRCPlus violations are introduced. Figure 1. Overall flow using a fast 2D pattern matching engine to enforce DRCPlus rules *ylai@cadence.com; phone 1 408 914-6701 Design for Manufacturability through Design-Process Integration IV, edited by Michael L. Rieger, Joerg Thiele, Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx rn I DtC DRC PSS I p I, +I Ofl4CcnsflMt McIS &gmrakin > VMJJCThe basis of this flow is the existence of a library of patterns that the router will check for in a given technology node. This paper will further illustrate a methodology for determining and using this library of patterns. A deck of patternbased rules can be easily defined, used, and modified as needed.Experimental results from this flow run on a routed block will be demonstrated.

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In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical Rows. After a brief description of the addressed flow, block budgeting challenges are detailed. Then, we explain why existing budgeting approaches are not adapted to fulfil these challenges. A new block budgeting algorithm is proposed. In order to derive relevant block constraints, this algorithm analyzes the design flexibility. This Flexibility Aware Budgeting (FAB) approach is then compared to some previous ones. Experiments based on commercial EDA tools and real designs show up to 55 % reduction in hierarchical flow run time and lead to a good flow timing closure. Block budgeting challengesAny physical synthesis solution has limitations on the size of circuits which can be handled in a single run. "Divide and Conquer" approaches have been introduced to overcome these limitations. In this kind of approach, large designs are sub-divided into smaller synthesizable sub-blocks. Fig. 1 depicts a typical timing-driven hierarchical flow. This flow starts with RTL synthesis and technology mapping.Resulting netlist is assumed to be too big or too complex to meet the specified performance. Thus, the design is partitioned into sub-blocks. These blocks are floorplanned upon the chip die. In fact, the floorplanning step includes design physical partitioning, blocks placement and inter-block net global routing. Then, blocks are optimized. Let's notice that partitioning technique not only permits to implement large designs, but also allows optimizing blocks concurrently, which can be precious to decrease time to market -this represents one more reason to use the hierarchical flow. Optimized blocks are reassembled at the top-level and top optimization is run. If chip constraints are not met, the whole process can be repeated. To implement sub-blocks, EDA tools need constraints. Blocks constraints are computed by the block budgeting step. The budgeting step derives blocks 10 constraints from the chip constraints. In order to speed up the hierarchical flow timing closure, the budgeting process has, first to assign feasible blocks constraints, and, second, to ensure that if blocks implementation succeeded, all chip constraints will be met. These two conditions qualify budgets quality.Another key point of block budgeting step stays in its low resources consumption (budgeting which runs slower than flat optimization is not interesting). If various delay budgeting approaches have been proposed to 0-7803-8702-3/04/$20.00 02004 IEEE. 26 1 Standard a i l s library RTL Synthesis I Fig. I. Typical hierarchical flow drive cell placement or net routing [ I ] [2] [3], there is only a few academic or industrial works dealing with IO constraints computing. [4]proposes an interresting RTL delay budgeting approach but reported that it needs an accurate area-time projection for each block; that is too much time consuming for our flow. [SI also presents an IO budgeting method for the timing-driven hierarchical flow. Unfortunately...