This paper proposes a new design check system that works in three steps. First, hotspots such as pinching/bridging are recognized in a product layout based on thorough process simulations. Small layout snippets centered on hotspots are clipped from the layout and similarities between these snippets are calculated by computing their overlapping areas. This is accomplished using an efficient, rectangle-based algorithm. The snippet overlapping areas can be weighted by a function derived from the optical parameters of the lithography process. Second, these hotspots are clustered using a hierarchical clustering algorithm. Finally, each cluster is analyzed in order to identify the common cause of failure for all the hotspots in that cluster, and its representative pattern is fed to a pattern-matching tool for detecting similar hotspots in new design layouts. Thus, the long list of hotspots is reduced to a small number of meaningful clusters and a library of characterized hotspot types is produced. This could lead to automated hotspot corrections that exploit the similarities of hotspots occupying the same cluster. Such an application will be the subject of a future publication.

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As technology processes continue to shrink, standard design rule checking (DRC) has become insufficient to guarantee design manufacturability. DRCPlus is a powerful technique for capturing yield detractors related to complex 2D situations 1,2 . DRCPlus is a pattern-based 2D design rule check beyond traditional width and space DRC that can identify problematic 2D configurations which are difficult to manufacture. This paper describes a new approach for applying DRCPlus in a router, enabling an automated approach to detecting and fixing known lithography hotspots using an integrated fast 2D pattern matching engine. A simple pass/no-pass criterion associated with each pattern offers designers guidance on how to fix these problematic patterns. Since it does not rely on compute intensive simulations, DRCPlus can be applied on fairly large design blocks and enforced in conjunction with standard DRC in the early stages of the design flow. By embedding this capability into the router, 2D yield detractors can be identified and fixed by designers in a push-button manner without losing design connectivity. More robust designs can be achieved and the impact on parasitics can be easily assessed. This paper will describe a flow using a fast 2D pattern matching engine integrated into the router in order to enforce DRCPlus rules. An integrated approach allows for rapid identification of hotspot patterns and, more importantly, allows for rapid fixing and verification of these hotspots by a tool that understands design intent and constraints. The overall flow is illustrated in Figure 1. An inexact search pattern is passed to the integrated pattern matcher. The match locations are filtered by the router through application of a DRC constraint (typically a recommended rule). Matches that fail this constraint are automatically fixed by the router, with the modified regions incrementally re-checked to ensure no additional DRCPlus violations are introduced. Figure 1. Overall flow using a fast 2D pattern matching engine to enforce DRCPlus rules *ylai@cadence.com; phone 1 408 914-6701 Design for Manufacturability through Design-Process Integration IV, edited by Michael L. Rieger, Joerg Thiele, Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx rn I DtC DRC PSS I p I, +I Ofl4CcnsflMt McIS &gmrakin > VMJJCThe basis of this flow is the existence of a library of patterns that the router will check for in a given technology node. This paper will further illustrate a methodology for determining and using this library of patterns. A deck of patternbased rules can be easily defined, used, and modified as needed.Experimental results from this flow run on a routed block will be demonstrated.