Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs.Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.

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Automated design tools produce layouts complying with all design rules (DRs). However, most wires are designed with minimum width, making them susceptible to random defect induced interruptions (opens). Spaces between wires are also often designed at minimum size, causing yield loss from random defect induced connections (shorts). SFF ("Spread -FattenFill") is a methodology to improve layout -specifically for routing metal layers -in terms of yield loss related to opens and shorts. Additionally, a novel fill concept improves metal density uniformity. In this paper, we will explain issues that were observed and addressed in the implementation on a real layout, and present results achieved in the first experiment on silicon.

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