Concurrent wire spreading, widening, and filling

Abstract

Automated design tools produce layouts complying with all design rules (DRs). However, most wires are designed with minimum width, making them susceptible to random defect induced interruptions (opens). Spaces between wires are also often designed at minimum size, causing yield loss from random defect induced connections (shorts). SFF ("Spread -FattenFill") is a methodology to improve layout -specifically for routing metal layers -in terms of yield loss related to opens and shorts. Additionally, a novel fill concept improves metal density uniformity. In this paper, we will explain issues that were observed and addressed in the implementation on a real layout, and present results achieved in the first experiment on silicon.

Interconnect Modeling: A Physical Design Perspective

“…Methodologies like design for manufacturability (DFM) or design for yield (DFY) have been intensively studied [7]- [10]. Examples are insertion of dummy metal fills for helping planarization during CMP [11], redundant vias (e.g., double vias) [7] for relieving via defects, and wire spreading/widening [8] for preventing metal shorts/opens. To reduce design-dependent variations, a methodology that incorporates a CMP simulator and lithography simulator in a design flow has been also studied [12].…”