Electro-optic sampling is performed on a high-speed silicon multiplexer integrated circuit using a gain-switched semiconductor laser and an external probe tip fabricated from GaAs. An approximate electrostatic model is used to calculate the dependence of the electro-optic modulation on the height of the probe tip above the circuit, the geometry of the circuit, and the dielectric constants of the probe tip material and the passivation layer (if any) on the circuit. The measured variation of the electro-optic modulation with probe tip height is in good agreement with the prediction of the model.

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latchup free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.

No abstract

No abstract

AT&T Bell L a b o r a t o r i e s Murray H i l l , N J 07974 PROCESSING We have fabricated very high speed, low power d e v i c e s and c i r c u i t s u s i n g a submicron NMOS technology. Our r e s u l t s i l l u s t r a t e t h e e l e c t r i c a l behavior of s i n g l e minimum s i z e d e v i c e s , a n d p r e s e n t t h e p e r f o r m a n c e of several submicron c i r c u i t s , s u c h a s r i n g o s c i l l a t o r s , a 3 GHz divide-by-two counter and a 90 MHz 16 X 16 m u l t i p l i e r .