This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for Crosscheck, Very-Low-Voltage, IDDQ and delay tests are also given.

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An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufactured (5491 devices), and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

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