Analysis and detection of timing failures in an experimental Test Chip

Franco, P.; Ma, S.C.; Chang, J.T.-Y.; Chu, Yi-Chin; Wattal, S.; McCluskey, E.J.; Stokes, Robert L.; Farwell, W.

doi:10.1109/test.1996.557127

Cited by 19 publications

(19 citation statements)

References 25 publications

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“…A timing-independent combinational (TIC) defect has both properties of a combinational defect and a timing-independent defect [4]. A defect that is either timing-dependent or pattern-dependent (non-combinational) is classified as a non-TIC defect.…”

Section: Collecting Accurate Iddq Measurements 2 Characterizing Vlvmentioning

confidence: 99%

“…Powell et al have analyzed some experimental data to correlate defects to functional and IDDQ tests [6]. In ITC'96, we only showed the statistics of defect classes [4]. In this paper, we identify the defect class of each die detected by the selected tests in the example.…”

Section: Collecting Accurate Iddq Measurements 2 Characterizing Vlvmentioning

confidence: 99%

“…Preliminary results based on only one clocking mode were also reported in ITC'95 [3]. In ITC'96, we reported the results on timing-dependent defects and also the defect population in each defect class [4]. Based on the results in [3] and [4], we selected 309 dies for further investigation.…”

Section: Introductionmentioning

confidence: 98%

“…This paper is part of a series that reported experimental results from a test chip [1] [2] [3] [4]. The design of the experiment and architecture of the test chip were described in ITC'95 [2].…”

Section: Introductionmentioning

confidence: 99%

“…In ITC'96, we reported the results on timing-dependent defects and also the defect population in each defect class [4]. Based on the results in [3] and [4], we selected 309 dies for further investigation. These dies were assembled in 120-pin ceramic pin grid array packages and tested with an Advantest T6671E VLSI Test System.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Experimental results for IDDQ and VLV testing

Chang

Tseng²,

Chu³

et al.

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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Section: Collecting Accurate Iddq Measurements 2 Characterizing Vlvmentioning

confidence: 99%

Section: Collecting Accurate Iddq Measurements 2 Characterizing Vlvmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Experimental results for IDDQ and VLV testing

Chang

Tseng²,

Chu³

et al.

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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Technology Overview

Design for AT-Speed Test, Diagnosis and Measurement

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Delay Fault Testing for VLSI Circuits

Krstić

Cheng

1998

Frontiers in Electronic Testing

256

120

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Unlike stuck-at fault testing, delay testing is closely tied to the test application strategy. This means that before tests for delay faults are derived it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.The focus of this chapter is on different test application schemes for combinational and sequential circuits. Techniques used for testing scan as well as non-scan designs are described. Also, the issue of testing high speed designs using slow testers is addressed and some of the currently available solutions to this problem are described.

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Analysis and detection of timing failures in an experimental Test Chip

Abstract: ABSTRACT

Cited by 19 publications

References 25 publications

Experimental results for IDDQ and VLV testing

Experimental results for IDDQ and VLV testing

Technology Overview

Delay Fault Testing for VLSI Circuits

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