In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

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In this work, arrays of two transistor (2T) and compact SONOS memory cells are presented together with an extensive reliability investigation. SONOS, which acronym stands f o r semiconductor-oxide-nitride-oxidesemiconductor, is a non-volatile memory concept, which has recently regained strong attention because floating gate flash reaches its scaling limits. The better scaling perspective together with the ease of inregration in a base line CMOS process makes SONOS an excellent candidate for embedded flash in frrture CMOS generations. This is especially true f o r the compact cell variant. which consists of a merged access gate (AG) and control gate (CG), giving extra advantages like smaller cell size and the reduction of short channel effects compared with the discrete two transistor variant.

In this paper, we present an investigation into the benefits DUV lithography for the manufacturing of Trench MOSFETs and its impact on device performance. We discuss experimental results for devices with a pitch size down to 0.6μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published Trench MOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3mΩ⋅mm 2 at a breakdown voltage of 30V (V gs =10V).

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