Reliability of embedded SONOS memories

Abstract

In this work, arrays of two transistor (2T) and compact SONOS memory cells are presented together with an extensive reliability investigation. SONOS, which acronym stands f o r semiconductor-oxide-nitride-oxidesemiconductor, is a non-volatile memory concept, which has recently regained strong attention because floating gate flash reaches its scaling limits. The better scaling perspective together with the ease of inregration in a base line CMOS process makes SONOS an excellent candidate for embedded flash in frrture CMOS generations. This is especially true f o r the compact cell variant. which consists of a merged access gate (AG) and control gate (CG), giving extra advantages like smaller cell size and the reduction of short channel effects compared with the discrete two transistor variant.

Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)

“…This is mainly due to the "poor" quality of the so-called default devices used for comparison (stoichiometric nitride). We obtained the best overall results with "standard" nitride [43], [44]. A stoichiometric Si N layer, formed with precursors SiH Cl (DiChloroSilane (DCS)) and NH , showed the best compromise between program/erase efficiency and reliability.…”

“…Concerning SONOS memories, it has been shown that a programming window well exceeding 2 V (in combination with a narrow distribution: mV) can be achieved using low program voltages (down to 11 V) and P/E times in the order of 1-100 ms [43], [44]. The erase saturation phenomenon (at high /long ), which could cause device degradation, has been addressed.…”

“…On the other hand, the excellent endurance of SONOS can be severely degraded if the erase conditions are chosen such that erase saturation occurs. Erase saturation easily occur if a "thick" (e.g., 2.5 nm) tunnel oxide is used, which results in severe window closure [44]. The same problem occurs if instead of a "thick" Fig.…”

“…The trapping properties of the nitride layer can be influenced by changing the stoichiometry, with different flow rates and/or precursors. Increasing the silicon content of the nitride layer increases the amount of silicon dangling bonds acting as trapping sites and, therefore, the program/erase efficiency [44]- [46]. Decreasing the silicon content of the nitride layer lowers the trap density and decreases efficiency, but it is claimed to improve the reliability [46], [47].…”

“…Most of the results described in this paper are measured on ONO layers with 2.2-nm bottom oxide, 6-nm DCS-based nitride and 8-nm HTO with anneal in combination with p-type gates, showing the best overall results. Other layer thicknesses and deposition conditions were processed but did not show improved overall characteristics [43], [44]. For the best compromise between program/erase efficiency and reliability, a stoichiometric Si N layer was used.…”