No abstract

In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

An improved model for charge injection through ONO gate stacks, that comprises carrier transport in the conduction band of the silicon nitride (Si3N4), is used to investigate the program/retention sequence of Si3N4 based (SONOS/TANOS) non volatile memories without making assumptions on the initial distribution of the trapped charge at the beginning of retention.We show that carrier transport in the Si3N4 layer impacts the spatial charge distribution and consequently several other aspects of the retention transient. The interpretation of the Arrehnius plots of the high temperature retention data, typically used to infer the trap depth from the retention activation energy is discussed. The model provides a simple explanation of the small threshold voltage increase observed during retention experiments of thick tunnel oxide ONO stacks.

No abstract

In this work, arrays of two transistor (2T) and compact SONOS memory cells are presented together with an extensive reliability investigation. SONOS, which acronym stands f o r semiconductor-oxide-nitride-oxidesemiconductor, is a non-volatile memory concept, which has recently regained strong attention because floating gate flash reaches its scaling limits. The better scaling perspective together with the ease of inregration in a base line CMOS process makes SONOS an excellent candidate for embedded flash in frrture CMOS generations. This is especially true f o r the compact cell variant. which consists of a merged access gate (AG) and control gate (CG), giving extra advantages like smaller cell size and the reduction of short channel effects compared with the discrete two transistor variant.