The use of a Si0.7Ge0.3 strained layer as an etch stop in silicon-based materials is reported. The etch rates were characterized through silicon and a 60 nm Si0.7Ge0.3 strained layer. The etch rate through undoped silicon was 17–20 nm/min, while the etch rate through the Si0.7Ge0.3 layer was 1 nm/min. After annealing the wafer to 850 °C for 30 min, transmission electron microscopy was used to show that strain in the alloy layer was only partially relieved, and that generated misfit dislocations were confined to the strained Si0.7Ge0.3 layer. The etch rate through the strained layer increased to 1.7 nm/min after this treatment, and was still perfectly functional as an etch stop.

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Bond and etch-back silicon on insulator was fabricated using a strain-selective etch and a novel etch stop consisting of a strained Si0.TGe0.3 layer deposited by molecular beam epitaxy. The process was used to fabricate a 200-350 nm silicon layer on insulator. A 350-nm silicon film on insulator fabricated by this technique was very lightly p-type with a carrier density of less than 1015 cm -3.Silicon on insulator is an important technology for the fabrication of devices that are high-speed, resistant to latch-up, and radiation-hard (1). Silicon on sapphire (SOS) has been the most widely used material for these applications, but the future generation of higher density integrated circuits is most probably incompatible with SOS materials, due to the highly defective silicon-sapphire interface, giving rise to a high density of defects propagating in the silicon film (2). For applications requiringra radiation-hardened material, consideration of the back-channel hardening at the buried oxide is also important. SIMOX (separation by implantation with oxygen) is a material that has been studied as a replacement for SOS (3). However, the difficulty in hardening the back channel of SIMOX is perhaps the most serious challenge of the utility of this technology for radiation-hard applications. Due to the nature of the process of SIMOX fabrication, the silicon-oxide interface is degraded during the oxide formation process. Other silicon-on-insulator (SOI) technologies also have problems with the buried oxide/silicon interface (4).Bond and etch-back silicon-on-insulator (BESOI) technology as an alternative to SIMOX for SOI has.the advantage of a cleaner oxide/silicon interface at the buried oxide (5, 6). This is because the buried oxide layer is fabricated with standard thermal oxides on the handle and prime wafers, followed by bonding the two wafers by heat-treatment in an oxidizing ambient. A schematic of the BESOI process is shown in Fig. 1. Either the prime wafer oxide, the handle wafer oxide, or both can be fabricated using radiation-hardening techniques before the bonding step is performed. After bonding, the prime wafer is thinned using a combined grinding and chemi-mechanical polishing, until the desired silicon film thickness is achieved.Recently, a silicon wafer bonding process technology was described that can produce high-quality SOI wafers in large quantities with silicon film thickness of 3 _+ 0.5 ~m (6). Using a modified thinning process that combines precision diamond machining and non-contact polishing, BESOI wafers with silicon film thickness of 0.6 -+ 0.2 ~m were successfully produced, and CMOS devices were fabricated on these wafers with high bulk mobilities and excellent radiation hardness (7). However, to produce BESOI wafers with silicon film thickness in the 0.25 ~m range, an etch stop is required in the silicon film thinning process. Heavily doped boron regions placed by diffusion or implantation into the silicon prime wafer have been reported to make an effective etch stop (5, 8). However, boron incorp...

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