The scaling of dry thermal oxides into the thin (<400 Å) range continues to motivate studies of the rapid initial oxidation rate of silicon unaccounted for by a linear-parabolic model. In this paper, silicon oxidation kinetics in this unresolved regime are studied by the incremental reoxidation of thin thermally grown and deposited silicon oxide layers on silicon. It is found that the reoxidation rates of thermally grown oxides in the thin regime rapidly decrease with increasing oxide thickness. In contrast, the reoxidation rates of deposited oxides are faster, and nearly thickness independent. It is also found that the reoxidation rates of thin thermal oxides can be significantly increased by inert thermal annealing. Existing thin-regime oxidation models are evaluated in light of these experimental findings, and it is concluded that only models invoking stress suppression of early oxidation kinetics can reconcile all experimental observations. In further support of a stress argument, the time and temperature effects of inert annealing are shown to be quantitatively consistent with a Maxwellian model for stress relaxation. Kinetic parameters extracted from experimental data are utilized to isolate specific mechanisms for the suppression of oxidation rate during the initial stages of silicon oxidation.

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We show that trapped holes at the Si-SiO2 interface account for all of the interface states generated by gate-positive irradiation of metal-oxide-silicon structures. The field-induced conversion of trapped holes to interface states is found to be the rate-limiting step in interface state buildup. Interface-state generation by hole trapping at the Si-SiO2 interface also plays a role for gate-negative irradiation. However, our experiments demonstrate an additional avenue for interface-state formation under these conditions. Holes created in the SiO2 layer are swept to the Al-SiO2 interface where they release positive ions. The transport of these ions to the Si-SiO2 interface under gate-positive field results in new interface states. Our data do not support models involving liberation of protons in the bulk of the SiO2 layer by hole transport through the oxide.

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area, of 8.61 //liil with conventional I-line lithography and 7.32 pin-with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a P. Pelley, photograph and biography not available at time of publication.

The birds beak profile for LOCOS-based isolations is shown to be a strong function of the patterned nitride width. In particular, the bird's beak height is found to be much smaller for intermediate widths (-0.6pm) than for either very wide or very narrow nitride lines. These width-dependent phenomena are explained using simulation. Furthermore, the use of Atomic Force Microscopy (AFM) is presented as a convenient approach for quantifying the 2-D encroachment effects common to all LOCOS-based schemes.