In this work, we propose transmitter and receiver circuits for high-speed, low-swing duobinary signaling over active-terminated chip-to-chip interconnect. In active-termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High-speed current-mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx-Rx pair is used to validate the proposed active-termination scheme. We also propose a duobinary precoder architecture suitable for high-speed operation and a low-power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 m Digital CMOS technology. The designed high-speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10 −15 . The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s.

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