Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design

Kalyan, T. Venkata; Mutyam, Madhu; Rao, P. Vijaya Sankara

doi:10.1109/vlsi.2008.15

Search citation statements

Order By: Relevance

Paper Sections

Select...

Microsystems1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2011

2015

Publication Types

Select...

Other2

Book1

Article1

Relationship

Self Cite0

Independent4

Authors

Journals

Cited by 4 publications

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The line energy model in a power-managed VLSI system, running at the operating state i, is given as [13] [14]: (10) In this equation, denotes the line (wire) switching activity factor and . Based on Equation (10), the line energy requirement increases monotonically with , as / is a positive value.…”

Section: Microsystemsmentioning

confidence: 99%

Repeater insertion in power-managed VLSI systems

Zarrabi

Al-Khalili

Savaria

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

In this paper, design space exploration methods for interconnect repeaters in DSM power-managed VLSI are proposed. These methods guarantee that the designed interconnects are energyoptimal, while they meet their performance objectives in all the system operating states. These methods take the dynamic output resistance characteristic of the repeaters into account, when the system operating voltage and/or operating frequency requirement changes. Utilizing the proposed design methods, a multi-cycle bus is designed for some performance targets. HSPICE simulations confirm that the designed bus is energy-optimal, and it meets its performance objectives in all the system operating states.

show abstract

Section: Microsystemsmentioning

confidence: 99%