Energy-aware analysis of electrically long high speed I/O links

Müller, Sebastian; Duan, Xiaomin; Schuster, Christian

doi:10.1007/s00450-012-0228-y

Cited by 2 publications

(5 citation statements)

References 5 publications

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“…2. With I R = 0 (since the receiver input impedance is included in the value of Z R ), the input impedance of the complete channel model becomes [21] …”

Section: A Equivalent Circuit For Power Evaluationmentioning

confidence: 99%

“…Fig. 3, using the calculation approach described in [21]. (a) Comparison of the total link input power P total = V 2 T · Re{Z −1 in }, for V T = 1 V for the configurations without and with ground vias.…”

Section: B Evaluation For a Simple Test Casementioning

confidence: 99%

“…The applied equivalent circuit neglects any power overhead in the transmitter and receiver circuits, aiming at a general evaluation of the relation between interconnect properties and input power rather than evaluations of specific circuit designs. The simplicity of the model permits a convenient evaluation in terms of ABCD parameters, which relate voltages and currents at transmitter and receiver as [21] V R…”

Section: A Equivalent Circuit For Power Evaluationmentioning

confidence: 99%

See 2 more Smart Citations

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Müller

Reuschel

Rimolo-Donadío

et al. 2015

IEEE Trans. Electromagn. Compat.

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This paper proposes a novel approach to evaluate design alternatives for high-speed links on printed circuit boards. The approach combines evaluations of signal integrity and link input power. For a comprehensive analysis, different link designs are made comparable through the application of identical constraints, with the link input power as the single figure of merit for a systematic, quantitative comparison of design alternatives. The analysis relies upon a combination of efficient physics-based via and trace models, statistical time-domain simulation, and an analytical input power evaluation, which allows it to handle links consisting of a large number of channels while fully taking into account interchannel crosstalk. The proposed approach is applied to study two fundamental design decisions at the PCB level-singleended versus differential signaling and signal-to-ground via ratios of 1:1 versus 2:1-for a link consisting of 2048 vias and up to 175 striplines with an aggregate data rate of 1 Tb/s. It is found that both design decisions have a considerable impact on the required input power of the link.Index Terms-Energy-aware analysis, high-speed links, printed circuit boards (PCBs), signal integrity (SI), via arrays.

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“…2. With I R = 0 (since the receiver input impedance is included in the value of Z R ), the input impedance of the complete channel model becomes [21] …”

Section: A Equivalent Circuit For Power Evaluationmentioning

confidence: 99%

Section: B Evaluation For a Simple Test Casementioning

confidence: 99%

Section: A Equivalent Circuit For Power Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Müller

Reuschel

Rimolo-Donadío

et al. 2015

IEEE Trans. Electromagn. Compat.

Self Cite

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show abstract

“…A typical data transmission that system includes driver, receiver, and interconnect is shown in Figure 1 below. While most effort has been concentrated on the on-chip circuit and interconnects' optimization [2][3][4][5][6][7][8], the energy-aware off-chip interconnect optimization in the transceiver circuit has not been investigated thoroughly so far [9,10]. The authors in [2][3][4] focused on energy-efficient on-chip interconnect design.…”

Section: Introductionmentioning

confidence: 99%

“…Secondly, voltage swing reduction at the transmitter due to the signal loss and crosstalk always degrades the receiver signal quality at the receiver. On the other hand, the authors in [9,10] are concerned with energy-efficiency evaluation for the off-chip interconnect, while the approach in [9] proposes an energy-aware analysis with analytical formulas using frequency-domain information. The authors in [10] provide a more comprehensive methodology to evaluate the energy efficiency of the I/O links.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems

Kim

2021

Applied Sciences

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In this paper, we propose an efficient design methodology for energy-efficient off-chip interconnect. This approach leverages an artificial neural network (ANN) as a surrogate model that significantly improves design efficiency in the frequency-domain. This model utilizes design specifications as the constraint functions to guarantee the satisfaction of design requirements. Additionally, a specified objective function to select low-loss and low-noise structure is employed to determine the optimal case from a large design space. The proposed design flow can find the optimum design that gives maximum eye height (EH) with the largest allowable transmitter supply voltage (VTX) reduction for minimum power consumption. The proposed approach is applied to the microstrip line and stripline structures with single-ended and differential signals for general applicability. For the microstrip line, the proposed methodology performs at a performance speed with 42.7 and 0.5 s per structure for the data generation and optimization process, respectively. In addition, the optimal microstrip line design achieves a 25%VTX reduction. In stripline structures, it takes 31.9 s for the data generation and 0.6 s for the optimization process per structure when the power efficiency reaches a maximum 30.7% peak to peak VTX decrease.

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Energy-aware analysis of electrically long high speed I/O links

Cited by 2 publications

References 5 publications

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Energy-Aware Signal Integrity Analysis for High-Speed PCB Links

Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems

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