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In this work, border traps located in SiO2 at different depths in 4H-SiC MOS system are evaluated by a simple and effective method based on capacitance-voltage (C-V) measurements. This method estimates the border traps between two adjacent depths through C-V measurement at various frequencies at room and elevated temperatures. By comparison of these two C-V characteristics, the correlation between time constant of border traps and temperatures is obtained. Then the border trap density is determined by integration of capacitance difference against gate voltage at the regions where border traps dominate. The results reveal that border trap concentration a few nanometers away from the interface increases exponentially towards the interface, which is in good agreement with previous work. It has been proved that high temperature 1 MHz C-V method is effective for border trap evaluation.

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