Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n-and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.As device dimensions continue to shrink into the nanometer length scale regime, fundamental physical limits and economics are likely to hinder further scaling according to Moore's law.1 New strategies including usage of new materials, innovative device architectures, and smart integration schemes are needed to extend the current capabilities beyond the end of the technology roadmap time frame. 2 "Bottom-up" approaches to nanoelectronics that utilize functional electronic nanostructures, 3-5 in particular 1D semiconductor nanowires, have the potential to stretch beyond the limits of traditional top-down manufacturing. However, the usual pick-and-place approaches of manipulating and aligning horizontally lying nanowires to fabricate prototype devices and the stringent lithography requirements have to be overcome before practical realization of integrated nanosystems. Furthermore, lithographic issues become paramount in further scaling of these nanowire-based planar devices, especially in defining ultra-small channel length in field-effect transistors (FETs).A proposed solution to these problems is to grow single crystal 1D nanowires directly on a device substrate with the major nanowire growth axis orthogonal to the substrate plane and to use this nanowire-integrated platform for direct device fabrication. Based upon this vertical generic configuration, an ensemble of nanoscale devices can be realized 6,7 ( Figure S1, Supporting Information). In the present work, we demonstrate the potential of this approach through the realization of a vertical surround-gate field-effect transistor (VSG-FET), which takes advantage of the vertical dimension unlike planar nanowire-based FETs and traditional metaloxide-semiconductor (MOS) FETs. The advantages of this vertical device configuration and enhanced device performance have been ad...

No abstract

We demonstrate seamless direct integration of a semiconductor nanowire grown using a bottom-up approach to obtain a vertical field-effect transistor (VFET). We first synthesize single crystalline semiconductor indium oxide (In 2 O 3 ) nanowires projecting vertically and uniformly on a nonconducting optical sapphire substrate. Direct electrical contact to the nanowires is uniquely provided by a self-assembled underlying In 2 O 3 buffer layer formed in-situ during the nanowire growth. A controlled time-resolved growth study reveals dynamic simultaneous nucleation and epitaxial growth events, driven by two competitive growth mechanisms. Based on the nanowire-integrated platform, a depletion mode n-channel VFET with an In 2 O 3 nanowire constituting the active channel is fabricated. Our unique vertical device architecture could potentially lead to tera-level ultrahigh-density nanoscale electronic, and optoelectronic devices.Bottom-up nanofabrication approaches involving direct interfacing and integration of low-dimensional nanostructures, in particular vertically aligned one-dimensional (1D) nanowires, could potentially provide an attractive solution to attain ultrahigh-density advanced nanoscale devices and 3D nanocircuitries. 1 To realize and maximize the true potential of these nanostructures for advanced applications in nanoelectronics and optoelectronics, reproducible synthesis of 1D nanowires with controlled directionality and morphology is critical. Equally important, a means of providing ideal and direct electrical interface to the nanowires 2 without disrupting their structural integrity would facilitate subsequent nanoscale device integration and realization of good device performance.Indium oxide is a direct wide band gap semiconductor (E g ∼ 3.55-3.75 eV) transparent oxide. 3 It finds several applications ranging from transparent conductive electrodes to electrochromic mirrors and gas sensors. 4 More recently, research has been conducted on indium oxide nanostructures, predominantly nanowires, for potential applications in highsensitivity sensor, optoelectronic, field-emission, electronic, and memory devices. [5][6][7] Various synthesis approaches have been demonstrated, which include vapor transport 8 and laser ablation 9 on a variety of substrates. However, common to other nanowire syntheses, growth directionality control (with respect to the substrate) and direct integration (on the same substrate) into functional devices remain as two significant challenges. To avoid the usual pick-and-place methods of manipulating and aligning horizontally lying nanowires to fabricate prototype testing platforms, 10,11 a proposed solution is to grow single crystalline nanowires epitaxially on a latticematched substrate with the major nanowire growth direction orthogonal to the substrate plane and to use this integrated platform for direct device fabrication. Ideally, the substrate also should be electrically conductive; however, potential substrates that meet both requirements are not readily available. Afte...