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The circuit element behavior during an active read-out approach is analyzed for the detection of the bit-state of a spin-transfer-torque (STT) switchable magnetic tunnel junction (MTJ) as a storage bit in a random access memory. Fundamentally, such read-out schemes detect the presence or absence of a hysteresis in the current-voltage characteristic of the MTJ depending on its magnetic configuration and the bias direction. A quantitative assessment is given in terms of the range of threshold distribution to be expected, and the read-out time one can achieve as it depends on various device parameters. The quantitative results given are based on an approximate macrospin model for the STT-switched MTJ.

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Significant progresses have been made in recent years in perpendicular spin torque transfer magnetic random access memory (pSTT-MRAM) technology development by many companies or organizations. Commercialization of pSTT-MRAM is more real today than ever in the long history of MRAM technology development. We have recently reported fully functional pSTT-MRAM chips and macros with sub-5ns writing speed based on 90nm and 40nm node CMOS technologies [1,2]. These technologies can be potentially used to replace current embedded non-volatile memories such as embedded flash memories or SRAM and be applies to energy efficient applications such as internet of thing (IOT). In this presentation, we will review recent progresses and discuss STT-MRAM scaling challenges for product at 28nm technology node and beyond in terms of integration schemes as well as magnetic and electrical transport properties. We will also discuss the potential solutions that we see for these challenges. References: [1] G. Jan, Symp VLSI Tech, 2014. pp 50-51. [2] Yu Lu et al, IDEM Technical Digest, 2015 (in press)