We propose a novel integrated fog cloud IoT (IFCIoT) architectural paradigm that promises increased performance, energy efficiency, reduced latency, quicker response time, scalability, and better localized accuracy for future IoT applications. The fog nodes (e.g., edge servers, smart routers, base stations) receive computation offloading requests and sensed data from various IoT devices. To enhance performance, energy efficiency, and real-time responsiveness of applications, we propose a reconfigurable and layered fog node (edge server) architecture that analyzes the applications' characteristics and reconfigure the architectural resources to better meet the peak workload demands. The layers of the proposed fog node architecture include application layer, analytics layer, virtualization layer, reconfiguration layer, and hardware layer. The layered architecture facilitates abstraction and implementation for fog computing paradigm that is distributed in nature and where multiple vendors (e.g., applications, services, data and content providers) are involved. We also elaborate the potential applications of IFCIoT architecture, such as smart cities, intelligent transportation systems, localized weather maps and environmental monitoring, and real-time agricultural data analytics and control.

The leisure and hospitality industry is one of the driving forces of the global economy. The widespread adoption of new technologies in this industry over recent years has fundamentally reshaped the way in which services are provided and received. In this paper, we explore some of the state-of-theart technologies currently employed in the hospitality industry and how they are improving guest experiences and changing the hospitality service platform. We also envision some potential future hospitality services we can expect as the Internet of things (IoT) technology keeps growing. We recognize that the technological backbone of many hospitality establishments needs to be overhauled in order to facilitate the changing landscape of technology in the modern world. We discuss some fundamental challenges that need to be overcome to institute a lasting futureproof solution for the hospitality industry. We also touch upon the problems these challenges pose for guests and hospitality service providers (HSP).

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The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23%-3.69% of the configurations obtained from fully exhaustive exploration while only exploring 3%-5% of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.Index Terms-Internet of Things (IoT), design space exploration, microarchitecture, tunable processor parameters, cycle-accurate simulator (ESESC), PARSEC and SPLASH2 benchmarksThe authors are with the

The need for application-specific design of multicore/manycore processing platforms is evident with computing systems finding use in diverse application domains. In order to tailor multicore/manycore processors for application specific requirements, a multitude of processor design parameters have to be tuned accordingly which involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient methodology for design space exploration. We evaluate our methodology over two search spaces small and large, using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH-2 benchmarks. For the smaller design space, we compare results obtained from our design space exploration methodology with results obtained from fully exhaustive search. The results show that solution quality obtained from our methodology are within 1.35% -3.69% of the results obtained from fully exhaustive search while only exploring 2.74% -3% of the design space. For larger design space, we compare solution quality of different results obtained by varying the number of tunable processor design parameters included in the exhaustive search phase of our methodology. The results show that including more number of tunable parameters in the exhaustive search phase of our methodology greatly improves solution quality.Index Terms-multicore/manycore processors, processor design parameters, design space exploration, cycle-accurate simulator (ESESC), PARSEC and SPLASH-2 benchmarks, parameter optimization ✦ • The authors are with the