Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 m, 0.25 m, and 0.35 m commercial CMOS processes. Their static I-V characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured by using ring oscillators agree well with the simulation results. The experimental results indicate about 40% speedup from 300 K to 4.2 K. A three-transistor DRAM cell for a Josephson-CMOS hybrid memory is also investigated at low temperature. The temperature dependence of the retention time shows an exponential increase at low temperatures. Based on the lowtemperature CMOS device model, we have developed short-delay CMOS amplifiers, which would amplify a 40 mV voltage input to CMOS voltage level with the propagation delay of about 100 ps, assuming the use of a 0.18 m CMOS process. We have measured the propagation delay of the CMOS amplifier by using a single-flux-quantum (SFQ) delay measurement system. This is a complete demonstration of the signal exchanges between SFQ and CMOS circuits at 4.2 K.

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated by using commercially available 0.25 m and 0.35 m CMOS processes and the NEC (SRL) 2.5 kA/cm2 and UC Berkeley's 6.5 kA/cm2 Nb processes for Josephson junctions. In order to simulate the low-temperature CMOS circuits, 4 K CMOS device models are established by extracting from experiments. The measurements made at 4 K include static I-V characteristics, gate capacitances and source and drain capacitances. Details of the modeling are found in a companion paper in this issue. Performance of the high-speed interface circuits is optimized by minimizing the parasitic capacitance loading. Both the functional test and high-speed measurement for the interface circuit will be discussed. The whole structure of the memory, including interface circuit, decoder, memory cell, and Josephson read-out circuit is proposed and fabricated. From simulation, a total access time well below 1 ns is expected. The power for the whole system is about 32 mW at 1 GHz. Plans for further power and access time reduction are described.

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated using a commercially available 0.18 m CMOS process and NEC-SRL's 2.5 kA cm 2 Nb process for Josephson junctions. The memory bit-line output signals are detected by ultra-low power, high-speed Josephson devices. The most challenging part of the memory system is the input amplifier; the performance of this amplifier is optimized by minimizing its parasitic capacitance loading. Functionality tests were reported at the ASC 2004, high-speed measurements are the focus of this paper. Most of the power dissipation in the memory system occurs in the input interface circuits. The power dissipation and delay for the interface circuit are reported. The delay time and power dissipation of the CMOS part (including drivers, decoders, and cells), which contributes most to the total access time of the hybrid memory, are measured. The relation of measurements to simulations will be presented. Plans for future designs to reduce power dissipation and latency are described.