History effects in 65-nm partially-depleted Silicon-onInsulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit designs. Introduction History effect is a challenge for partially-depleted (PD) SOI CMOS circuit designs. With the device body region floating, the difference in charging time between the channel and body introduces history dependencies (and thus uncertainty) in gate switching speed. This floating body effect may degrade circuit performance. From a device development standpoint, it is crucial to accurately characterize this behavior and to optimize it across bias voltage, threshold voltage, and dimension without degrading other performance metrics. Fig. 1 shows NFET body potential as a function of time for ISW (an initial switching event after extended inactivity) and 2SW (a second switching event immediately after ISW) cases. The body potential VBS changes as the device switches between the "on" state (i.e. VGS=VGD=VDD) and "off' state (i.e. VDG =VDS=VDD). As derived in [1][2], AVAC depends on the ratio of gate to body and junction capacitances. The equilibrium VBS

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