Optimizing History Effects in 65nm PD-SOI CMOS

Liang, Qicong; Kawamura, Takahiro; Ketchen, M. B.; Kawanaka, S.; Pelella, M.M.; Robertson, Donald S.; Bhushan, M.; McStay, K.; Freeman, G.; Miyamoto, Koji; Leobandung, E.; Huang, Shih-Fen

doi:10.1109/soi.2006.284450

Cited by 4 publications

(3 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We refer the reader to references [1][2][3][4][5] for details on the various parameters that impact body voltage behavior. Figure 4(b) shows two scenarios for the NFET and PFET body voltage initial values and swings for an inverter configuration.…”

Section: Soi History Effect (He) Modelingmentioning

confidence: 99%

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Aarestad

Lamech

Plusquellic

et al. 2011

Proceedings of the 48th Design Automation Conference

View full text Add to dashboard Cite

Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this paper, we propose a flush delay technique for measuring both regional delay variations and SOI history effect and validate the method using a test structure fabricated in a 65 nm SOI process.

show abstract

Section: Soi History Effect (He) Modelingmentioning

confidence: 99%

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Aarestad

Lamech

Plusquellic

et al. 2011

Proceedings of the 48th Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD SOI devices possess several unique behaviors that do not exist in bulk devices, such as kink effect, [1][2][3] self-heating effect, [4][5][6] history delay effect, 7,8 and pass-gate leakage. 9,10 As metaloxide-semiconductor field effect transistor ͑MOSFET͒ sizes are scaled down to the nanoscale regime, leakage current is one of the key challenges faced by designers when attempting to realize devices that provide high performance and high scalability.…”

mentioning

confidence: 99%

Optimization of Back Channel Leakage Characteristic in PD SOI p-MOSFET

Chen

et al. 2010

J. Electrochem. Soc.

View full text Add to dashboard Cite

The impact of back channel leakage ͑BCL͒ is thoroughly investigated when scaling down partially depleted ͑PD͒ silicon-oninsulator ͑SOI͒ devices. Back channel voltage is introduced as an indicator for monitoring the behavior of BCL. In addition to front-gate devices, back-gate devices also suffer from short channel effect. Finally, BCL can be successfully suppressed by optimizing process parameters such as the Si remains, the well implant, and the SOI thickness.Silicon-on-insulator ͑SOI͒ complementary metal oxide semiconductor ͑CMOS͒ has been widely used in recent years for its better device performance and scalability. Partially depleted ͑PD͒ SOI has a similar device structure to a bulk device. As a consequence, PD SOI can be fabricated using a standard bulk CMOS process. SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD SOI devices possess several unique behaviors that do not exist in bulk devices, such as kink effect, 1-3 self-heating effect, 4-6 history delay effect, 7,8 and pass-gate leakage. 9,10 As metaloxide-semiconductor field effect transistor ͑MOSFET͒ sizes are scaled down to the nanoscale regime, leakage current is one of the key challenges faced by designers when attempting to realize devices that provide high performance and high scalability. In PD SOI, there is an additional leakage component other than the common leakage currents of a bulk device, such as junction leakage, gate induced drain leakage, and Drain Induced Barrier Lowering ͑DIBL͒. This leakage component is called back channel leakage ͑BCL͒, which is the subthreshold leakage of a back channel MOSFET. Figure 1 shows the cross section of a PD SOI device with a front-gate channel and a back-gate channel. When the back-gate channel is not turned off properly, BCL can contribute an additional leakage current to the device, resulting in a higher off-state leakage current. Several previous studies are focused on radiation induced BCL. [11][12][13][14][15] It was reported that back-gate bias could suppress the BCL and reduce its impact on circuits. [16][17][18] Consequently, it is important to characterize the BCL behavior and develop a strategy to effectively suppress the BCL.In this paper, the BCL has been characterized by applying a back-gate bias. In the Characterization and Methodology section, we present a methodology for monitoring the BCL. The back-gate device also suffers from the short channel effect ͑SCE͒. In the Results and Discussion section, we discuss the methods used to minimize the BCL of p-MOSFET. Finally, the BCL can be fully controlled in a 45 nm PD SOI process by optimizing three key process parameters: Si remains, well dose, and SOI thickness. Characterization and MethodologyThe devices used in this study are fabricated using a 45 nm SOI process. 19 Figure 2 shows the Id-Vg curves for a p-MOS ͑W/L = 0.6/0.04 um͒ at different back-gate biases ranging from 0 to 30 V. A large subthreshold leakage current occurs when the back-gate ...

show abstract

“…SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD-SOI devices possess several unique behaviors that do not exist in bulk devices such as kink effect, [1][2][3] self-heating effect, [4][5][6] history delay effect, 7,8 and pass-gate leakage. 9,10 Those effects have been actively studied and modeled.…”

mentioning

confidence: 99%

The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI

Luo

et al. 2009

J. Electrochem. Soc.

View full text Add to dashboard Cite

Body-to-body leakage ͑BBL͒ current in a partially depleted silicon-on-insulator ͑PD-SOI͒ device is increased significantly as polyspacing ͑PS͒ is reduced in technology scaling. We found out that the BBL has a great impact to Vt variation. We have demonstrated that the BBL can be minimized drastically by implant optimization. The dependence of the BBL on silicon film thickness, e-SiGe structure, and dopant diffusivity is also discussed in this paper. The layout effect of the BBL current in PD-SOI devices has been characterized with different PSs, device widths, and polylengths. Finally, we have demonstrated that the BBL current can be reduced below junction leakage level.Silicon-on-insulator ͑SOI͒ complementary metal oxide semiconductor ͑CMOS͒ has been widely used recently due to its better device performance and scalability. Partially depleted silicon-oninsulator ͑PD-SOI͒ has a similar device structure to a bulk device. As a consequence, the PD-SOI can be fabricated in a standard bulk CMOS process. SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD-SOI devices possess several unique behaviors that do not exist in bulk devices such as kink effect, 1-3 self-heating effect, 4-6 history delay effect, 7,8 and pass-gate leakage. 9,10 Those effects have been actively studied and modeled. For the two stack PD-SOI devices sharing a common diffusion area, the bodies of the two devices are isolated by a common source/drain ͑S/D͒ junction. If the common S/D junction does not abut the buried oxide ͑BOX͒, a leakage path is formed between the two bodies. The body-to-body leakage ͑BBL͒ induces body potential change and Vt shift, as reported in Refs. 11 and 12. Besides, ac performance is degraded because of the increase in the S/D junction capacitance. In an advanced SOI technology, aggressive scaling of the junction depth leads to a significant increase in the BBL current. The BBL can have the following adverse effects on circuit operation: ͑i͒ Higher junction capacitance due to the larger junction area, ͑ii͒ Vt shift due to the change in body potential, and ͑iii͒ failure of circuit function if device Vt is significantly changed. As a result, the BBL effect must be taken into consideration when optimizing the S/D junction profile in PD-SOI devices.The accuracy of device modeling becomes increasingly important in modern circuit design. Although several attempts have been made on the modeling and simulation of the BBL, very few experimental results have been reported. The BBL effect also depends on the device geometries such as polygate spacing. The geometry effect must also be taken into consideration when optimizing the S/D junction profile.This paper presents the experimental and simulation results of the BBL effect and its dependences on back-gate bias, polygate spacing, device width, silicon layer thickness, and S/D implant conditions. The impact of the Vb shift to circuit function caused by the BBL in stack PD-SOI devices has bee...

show abstract

Optimizing History Effects in 65nm PD-SOI CMOS

Cited by 4 publications

References 2 publications

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Optimization of Back Channel Leakage Characteristic in PD SOI p-MOSFET

The Characteristics and Control of Body-to-Body Leakage Current in PD-SOI

Contact Info

Product

Resources

About