Silicon Carbide power MOSFETs are used in numerous studies to improve the efficiency or the performance of power electronic converters. However, the gate-oxide technology weakness is a main reliability issue of Silicon Carbide MOSFET transistors. The threshold voltage shift is a critical phenomenon that addresses the reliability of industrial power applications. It is important to have a better understanding of the phenomena implied in the gate threshold voltage shift. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide stress is studied and discussed in this paper. Complementary testing was performed with dynamic reliability and gate oxide characterizations, such as the charge pumping technique. The results obtained are used to add insight to the current discussion of SiC MOSFET robustness. Additionally, test benches and measurement protocols are detailed.

The threshold voltage instability is a main reliability issue of Silicon Carbide MOSFET transistors. It is a critical parameter when it comes to give a failure in time rate for industrial power applications. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide degradation is studied and discussed in this paper. Complementary testing was performed with dynamic reliability on the gate and the results obtained are used to add insight to the current discussion of SiC MOSFET reliability standards. Additionally, test bench and characterization protocols are detailed.