Measurement and analysis of SiC-MOSFET threshold voltage shift

Han

et al. 2021

Adv Elect Materials

Cl, Br, or I) where a monovalent molecular cation and divalent metal cation are occupied in the A-site and the B-site, respectively to active layers in various ways. [3] Thanks to their defect tolerance properties, many researchers have tried to control charge transport behaviors by minimizing defects that possibly exist in grain boundaries (GBs), interfaces, and structural imperfections. [4][5][6][7][8] In early research, single-crystal methyl-ammonium lead iodide (MAPbI 3 ) TFTs were reported whose maximum hole mobility (μ h ) was 4.7 cm 2 V −1 s −1 with bottom-gate bottom-contact (BGBC) configuration by Yu et al. [7] Recently, Zhu et al. reported 2D phenethylammonium tin iodide ((PEA) 2 SnI 4 ) TFTs with the methods of enlarging grain sizes by mixing the Lewis-based solvents and passivating iodide vacancies by oxygen treatment. [8] Comprehensively, these trials were based on optimizing morphologies of the films to overcome the Schottky barrier which is detrimental to the injection in the channel layers during the switching operation. Despite their feasible controllability, they still have unresolved problems in adjusting TFTs due to weak charge conduction, environmental instabilities, and gate-screening effect from ion migration. [9][10][11] Here, the defect-controlled inorganic halide perovskites (IHPs) were investigated. IHPs consisting of the extensive inorganic framework are considered to be alternative semiconducting materials, allowing TFTs to be operated for a longterm period and better conduction. [12,13] Among them, we chose cesium lead iodide (CsPbI 3 ) that has high intrinsic carrier mobility and diffusion length. [14] Even at the experimental value of the carrier mobility of the cubic (α)-CsPbI 3 film through a terahertz spectroscopy method, a charge carrier mobility of CsPbI 3 is above 30 cm 2 V −1 s −1 . [15] This value is higher than that of MAPbI 3 , MAPbI 3-x Cl x , FASnI 3 , FAPbBr 3 , and PEASnI 4, considering that the carrier mobility measurement method is the same. [16] Furthermore, extrinsic point defects can be formed by adding various additives, which can further improve the carrier mobility of the conventional α-CsPbI 3 . This electrically promising potential of α-CsPbI 3 is the main reason why we choose the active layer in TFT.However, high hole-doped HPs can be disadvantageous to TFT devices due to the difficulty to inhibit an overabundance of the hole carriers even in the off-state operation. [17] This can So far, it has been difficult to fabricate thin-film field-effect transistors (TFTs) based on inorganic halide perovskites (IHPs) due to their phase-instability and uncontrollable trap density. Here, the bottom-gate bottom-contact structured p-type TFTs are presented using the optimized IHP in the active layer. The stable cubic-CsPbI 3 phase is successfully synthesized by doping bismuth iodide and reduced defect densities by adding potassium bromide. The IHP TFTs based on the tailored cubic-CsPbI 3 show high hole mobility of ≈10 cm 2 V −1 s −1 , an on-off current ratio of 10 3 , a...

Section: Resultsmentioning

confidence: 99%

High Hole Mobility Inorganic Halide Perovskite Field‐Effect Transistors with Enhanced Phase Stability and Interfacial Defect Tolerance

Han

et al. 2021

Adv Elect Materials

J. Micromech. Microeng.

“…To examine the impact of traps, gate leakage currents, I GDD keeping source terminal floating, and I GSS keeping drain terminal floating are plotted in figures 4(b) and (c), respectively [36]. The characteristics for acceptor-like traps, and donor-like traps are plotted after carrying out TCAD simulations at three random source (drain) voltages for I GDD (I GSS ) in millivolts to consider the floating terminals.…”

Section: Effect Of Trap Concentration and Temperature On Transfer Cha...mentioning

confidence: 99%

Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs

Deb¹,

Goswami²,

Baruah³

et al. 2022

This article reports the response of a silicon-on-insulator (SOI) TFET to the presence of semiconductor/ gate dielectric interface traps. A systematic strategy is designed keeping in view different parameters which are related to the gate of the device. Acceptor-like traps, and donor-like traps with Gaussian distribution are considered at the said interface for the entire analysis. Sensitivity % is taken as a figure of merit which measures the deviation of the drain current in presence of traps from the cases with no traps. The effect of temperature on interface traps, and the effect of interface traps on gate leakage current are analyzed. The acceptor-like traps are found to affect the on-state regime, and the donor-like traps are found to affect the ambipolar regime. Analyses on gate-drain underlap, gate-source overlap, shift of entire gate over the device, and gate work-function suggest that the gate electrode plays an important role in determining the sensitivity of the TFETs. Furthermore, noise spectral densities in presence of flicker, diffusion, and monopolar generation-recombination noise sources, and interface traps are reported.

“…In practical applications, the off-state negative V gs is expected to be lower, enabling a wider voltage safety margin between V gs spike and V th to avoid fault turn-on case of devices. However, when a lower negative V gs is used as turn-off voltage, there is an obvious subthreshold voltage hysteresis (∆V th,sub ) case in commercial 4H-SiC MOSFEF, [4,5] especially in 4H-SiC trench MOSFET. [6] The ∆V th,sub causes a drain current overshoot at high dV /dt, as the overdrive V gs -V th is momentarily higher.…”

Section: Introductionmentioning

confidence: 99%

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs*

Chen¹,

Shi²,

Li³

et al. 2021

Chinese Phys. B

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.