An atomistic model for the transformation of amorphous (α) to crystalline silicon films while in contact with a crystalline substrate is presented. The atomic structure of the {100}, {110}, and {111} surfaces is examined and related to the observed interface migration rates. The assumption that for an atom to attach successfully to the crystal it must complete at least two undistorted bonds, leads to the prediction that the {100} amorphous/crystalline interface should advance fastest and the {111} slowest. The origin of crystal defects is discussed in terms of the atomistic recrystallization mechanism. Microtwins are found to be a logical consequence of crystallization on the {111} surfaces but are not expected to form on any other interface. Once microtwins are formed they can increase the recrystallization rate of a {111} surface. This phenomenon is both described in the model and experimentally observed.

Oxidation of silicon wafers containing lattice damage at the surface normally results in the formation of extrinsic stacking faults. Optical microscope investigation following decorative etching shows that on certain specimens the faults have a straight line appearance while on others the ends of the defect are much enlarged giving a ‘‘dog-bone’’ shape. Analytical electron microscopy investigation confirmed that the dog-bone shaped faults were decorated with two types of precipitates near their edges, colonies and plate. Both resided on the (111) fault planes and extended over several thousand angstroms. Precipitate diffraction spots were not found due to the small volume fraction, but translational Moiré fringes were observed for certain matrix g vectors, thus aiding in the crystallographic analysis. Energy dispersive x-ray analysis revealed that colony precipitates were due to Ni and Cu contamination while plate precipitates were due to Ni. Crystal structures for both were determined to be NiSi2 type silicides.

Ion implantation damage that transforms to crystallographic defects such as dislocation loops or stacking faults with heat-treatments is unavoidable in VLSI device fabrication. Dislocation loops were introduced into three different regions of p § junction such as the p § the depletion, or the n region by Si implantation followed by annealing. Stacking faults were introduced into the p § region or extended into the depletion region of p § junction by Si implantation followed by oxidation. Locations, densities, and characteristics of the extended defects were scrutinized with transmission electron microscopy (TEM). In forward bias, diodes having dislocation loops still show diffusion currents with the ideality factor equal to 1, regardless of their locations, only increasing the ohmic resistance at forward bias higher than 0.5V. In addition, dislocation loops in the depletion or the n region caused higher diffusion current levels than control diodes which did not have dislocation loops. In reverse bias, dislocation loops in the n region caused the smaller generation current than those in the depletion region, whereas dislocation loops in the p § region caused current levels as low as control diodes. Stacking faults in the p § region functioned similarly to dislocation loops in the p § region except for showing higher ohmic resistance than dislocation loops, even though the densities of the former were much lower than those of the latter. Only stacking faults extending into the depletion region caused the large leakage currents which degrade the diode functions.In Si VLSI device fabrication, ion implantation is a very common method for controlling the doping profiles and concentrations. The main problem with this technology is the introduction of surface damage. Damage induces extended defects such as dislocation loops or stacking faults in the subsurface of the silicon substrate during subsequent heat-treatment in device fabrication (1). Normal extended defect sizes vary from 0.01 to 10 ~m which can be identified with ease using the TEM.The crystallographic structure of dislocations in silicon is well understood (1) and the electrical impact of dislocations on the diode are summarized by Matare (2). The primary dislocations which are introduced during crystal growth were believed to provide paths for the locally enhanced diffusion of phosphorus, which causes leakage in the diode (3). The high leakage current was assumed to be related to the presence of dislocations in or near the n region of the p-n junction (4). Electrical shorts due to dislo~ cations were studied for bipolar transistors (5-7) and for MOSFET (8).It has been pointed out that dislocation loops were generated at the highest damaged region which is slightly shallower than the highest ion concentration peak position which defines the p-n junction boundary (9). Lasky (10) intentionally located dislocation loops by this way in the p region, which is made by B implantation in n-type substrates, and observed the leakage currents under reverse bias. Another...