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We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO, interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO,, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Biassputtered SiO, is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A h Z to 5000 A/cmz, fabricated over NbN ground planes up to 1 pm thick, exhibit low subgap leakage (V, -15 mV at 10 K) and high sumgap voltage (V, = 4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.

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