Superconductive multi-chip module process for high speed digital applications

Abelson, L.A.; Elmadjian, R.; Kerber, G.L.; Smith, Andrew D.

doi:10.1109/77.621778

Cited by 18 publications

(6 citation statements)

References 5 publications

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“…Project goals include sub-ns access time, high bandwidth, low power and 16 kbit cm −2 density. This density, achievable using TRW's conservative but stable 2.5 µm, 2 kA cm −2 Nb foundry process [7], is hardly within sight of semiconductor SRAM. Nevertheless, it does scale to meet HTMT requirements given the development of a 0.8 µm, 20 kA cm −2 process [8].…”

Section: Introductionmentioning

confidence: 93%

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Towards a 16 kilobit, subnanosecond Josephson RAM

Herr¹,

Eaton²

1999

Supercond. Sci. Technol.

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A critical component of ultrahigh-speed Josephson logic systems is compatible memory. We are developing a fast Josephson memory that could be used as a small memory or first-level cache. Performance goals include sub-ns access and cycle time, 16 kbit cm-2 integration scale, low power consumption and appreciable yield. Initial test results on circuits fabricated in TRW's standard Nb integrated circuit process indicate that all these goals may be achieved. A 5 bit parallel decoder and 1 kbit memory array have been tested at 0.5 GHz. The maximum operating frequency of the memory array was limited by the test equipment. Circuit density is consistent with 16 kbit cm-2. The top-level architecture has been chosen to achieve high throughput and low skew. The architecture is word organized, multiported and interleaved.

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Section: Introductionmentioning

confidence: 93%

“…A stand-alone 5-bit decoder has been fabricated and tested using TRW's standard Nb process [7]. The width of each NOR gate is 44 µm; total dimensions are 1.5×0.3 mm 2 .…”

Section: Decodermentioning

confidence: 99%

Towards a 16 kilobit, subnanosecond Josephson RAM

Herr¹,

Eaton²

1999

Supercond. Sci. Technol.

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“…Integration of Nb in multi-layer back end of line has been developed over the years for large-scale single flux quantum circuits [24,25] and is now the main part of routing in multi-chip modules and interposers dedicated to superconducting qubits [11]. Multichip modules made from NbN routing have also been previously studied for high-speed digital applications [26]. NbN is now incorporated in bumping technologies for 3D quantum architectures [27] or in qubit readout elements such as resonators [28] thanks to its large kinetic inductance.…”

Section: Demonstrator Presentationmentioning

confidence: 99%

Superconducting routing platform for large-scale integration of quantum technologies

Thomas

Michel

Deschaseaux

et al. 2022

Mater. Quantum. Technol.

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To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridation of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.

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“…In addition to time savings, the sacrificial process is cleaner without any residue than classical metal lift-off. When regular photoresist is lifted off using acetone or other chemicals [7,8], the lift-off process leaves some residue of metal particles on the substrate [21]. However, using the sacrificial SU-8 process, there is no visible residue on the surface (figure 5).…”

Section: Analysis Of the Peel-off Processmentioning

confidence: 99%

A sacrificial SU-8 mask for direct metallization on PDMS

Patel

Kaminska

Gray

et al. 2009

J. Micromech. Microeng.

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A new fabrication technology utilizing SU-8 as a sacrificial mask for metallization of the PDMS surface is presented. The sacrificial SU-8 layer process offers superior performance for reliable and repeatable metallization on the PDMS layer. Sacrificial SU-8 masks from 45 µm to 250 µm thickness are successfully fabricated on the PDMS layer to pattern gold on the PDMS surface. These layers are successfully peeled off from the PDMS surface after a metal deposition step. Metal lines from 10 µm to 500 µm wide and 1 mm to 50 mm long are successfully patterned and tested. Furthermore, the sacrificial SU-8 mask can be removed within minutes to realize metal patterns on the PDMS surface and does not leave any residue after removal of the SU-8 layer. As this new process is intended for use in fabrication of microfluidic and biomedical microdevices, electrodes of an electro-enzymatic glucose sensor are presented to demonstrate the technology.

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Superconductive multi-chip module process for high speed digital applications

Cited by 18 publications

References 5 publications

Towards a 16 kilobit, subnanosecond Josephson RAM

Towards a 16 kilobit, subnanosecond Josephson RAM

Superconducting routing platform for large-scale integration of quantum technologies

A sacrificial SU-8 mask for direct metallization on PDMS

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