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This paper describes t h e key technology t o scale down the Flash EZPROM cell, which has a conventional s e l f -a l i g n e d d o u b l e poly-Si s t a c k e d s t r u c t u r e .I t is c l a r i f i e d experimentally t h a t Flash memory c e l l w r i t t e n and erased by Fowler-

A NAND structured memory cell with 2.2 times 1.05 umz size per bit, based on a 0.6 um design rule, has been developed for 16Mb Flash EEPROMs. The cell size is about 6 4 % of the smallest 16Mb EPROM cell so far reportedr1'.An extremely small cell can be realized by the following technologies; 1) newly developed 0.3 um space self-aligned stacked gate patterning, 2) NAND structured cell array which contains 16 memory transistors in series, 3) high voltage field isolation technology used to isolate neighboring bits. First and second technologies reduce the length of the cell by 67.6%, compared with conventional NAND structured cell, using same design rule, and the third technology reduces the width by 84.6%. developed in order to achieve a cell area reduction without stressing the fabrication technology[2-51. This paper describes an advanced NAND structured cell and several novel technologies to produce EEPROMs of 16 Mbit and beyond. PROCESS TECHNOLOGY and ELECTRICAL PER-FORMANCE 0.3um word line spacingIn the NAND structured cell, the space between neighboring stacked gate word lines can be reduced to zero theoretically, because neither contact hole nor source line is required between word lines. A novel word line patterning process has reduced this idle space from 0 . 6 um to 0.3 um with a 0.6 um design rule (Fig.1).The main process steps are as follows. First, Silicon Nitride (SiN) is deposited on the 2nd Poly-Si INTRODUCTION layer, and SiN is etched to striped pattern, of which line/space is 0.6 um/1.2 Recent progress in computers requires um. Next, resist line is formed in a further efforts in developing higher space of the SiN line. The resist line density EEPROM memories. Small chip size width is 0.6 um and the space between is essential requirement for multiSiN line and the resist line is 0.3 um. megabit devices. In order to improveThe stacked double poly-Si layers and performances and manufacturability of interpoly dielectric are etched simulnew EEPROM generations, innovative techtaneously using SiN and resist mask. nologies must be investigated. NANDThe second and first poly-Si layer serve s t r u c t u r e d m e m o r y c e l l h a s b e e n as control gate and floating g a t e , CH2865-4/90/0000-0103 $1.00 0 1990 IEEE IEDM 90-103 respectively. The stacked poly-Si g a t e s f o r m w o r d l i n e s o f w h i c h l i n e / s p a c e b e c o m e s 0.6 u m / 0 . 3 um (Fig.2,3). NAND structured cell with 16 memory transistors in seriesTo reduce the area occupied by contact hole, select transistors and source line per bit, the number of bits connected in one NAND structure increases from 8 to 16 in the advanced NAND EEPROM. The cell size of 16 bit NAND is reduced by 20% ,compared with that of 8 bit NAND (Fig.4). The cell read current of 16 bit NAND becomes smaller than 8 bit NAND, because sum of channel resistance becomes large. However, cell read current is m a i n t a i n e d m o r e t h a n 7 u A if threshold voltages of the written cells are c o n t r o l l e d f r o m 0 . 5 V to 3 . 0 V (Fig. 5). 2.2um bit...

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