A reliable bi-polarity write/erase technology in flash EEPROMs

Abstract

This paper describes t h e key technology t o scale down the Flash EZPROM cell, which has a conventional s e l f -a l i g n e d d o u b l e poly-Si s t a c k e d s t r u c t u r e .I t is c l a r i f i e d experimentally t h a t Flash memory c e l l w r i t t e n and erased by Fowler-

Effects of Interface Trap Generation and Annihilation on the Data Retention Characteristics of Flash Memory Cells

“…From (5), we can obtain (8) If we consider (9) from (4) we can obtain an distribution equation as (10) It is manifest from Fig. 9…”

“…In the past, most studies have been focused on the stress-induced leakage current (SILC) phenomenon to describe the data retention characteristics as a trap-assisted tun- neling (TAT) [9]- [13]. However, as the dimensions of the flash cells are scaled down, we have found that an annihilation phenomenon of interface states ( , : hydrogen, etc.)…”

A New Embedded One-Time-Programmable MNOS Memory Fully Compatible to LTPS Fabrication for System-on-Panel (SOP) Applications

“…By adapting channel FN tunneling write [9], the cell is able to retain data for more than ten years at 125 • C without any significant read current shift.…”

A quantitative analysis of stress-induced leakage currents and extraction of trap properties in 6.8 nm ultrathin silicon dioxide films

“…6,7 These stress-induced leakage currents increase with decreasing oxide thickness, 1 and set therefore a lower limit for a further reduction of the gate oxide thickness in FLASH memory based devices. 8 There is general agreement that trap-assisted tunneling is caused by the generation of traps inside the oxide during high-voltage stressing and lead to the observed stressinduced leakage currents.…”