No abstract

Silicon nanowire field effect transistor (FET) sensors have demonstrated their ability for rapid and label-free detection of proteins, nucleotide sequences, and viruses at ultralow concentrations with the potential to be a transformative diagnostic technology. Their nanoscale size gives them their ultralow detection ability but also makes their fabrication challenging with large sensor-to-sensor variations, thus limiting their commercial applications. In this work, a combined approach of nanofabrication, device simulation, materials, and electrical characterization is applied toward identifying and improving fabrication steps that induce sensor-to-sensor variations. An enhanced complementary metal-oxide-semiconductor-compatible process for fabricating silicon nanowire FET sensors on 8 in. silicon-on-insulator wafers is demonstrated. The fabricated nanowire (30 nm width) FETs with solution gates have a Nernst limit subthreshold swing (SS) of 60 ± 1 mV/decade with ∼1.7% variations, whereas literature values for SS are ≥80 mV/decade with larger (>10 times) variations. Also, their threshold voltage variations are significantly (∼3 times) reduced, compared to literature values. Furthermore, these improved FETs have significantly reduced drain current hysteresis (∼0.6 mV) and enhanced on-current to off-current ratios (∼10). These improvements resulted in nanowire FET sensors with the lowest (∼3%) reported sensor-to-sensor variations, compared to literature studies. Also, these improved nanowire sensors have the highest reported sensitivity and enhanced signal-to-noise ratio with the lowest reported defect density of 2.1 × 10 eV cm, in comparison to literature data. In summary, this work brings the nanowire sensor technology a step closer to commercial products for early diagnosis and monitoring of diseases.

A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on (110)-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2nm have been demonstrated, with substantial enhancement of pFET drive current at L,&8Gnm. IntroductionIt is known that hole mobility is more than doubled on (110) silicon substrates with current flow direction along <1 lo> [I -31 compared with conventional (1 00) substrates. However electron mobility is the highest on (100) substrates (Fig. I). To fully utilize the advantage of the carrier mobility dependence on surface orientation, in the present work we have developed a new technology to fabricate CMOS on hybrid substrates with different crystal orientations, with nFETs on silicon of (100) surface orientation and pFETs on (1 IO) surface orientation. High performance CMOS devices using 90nm technology with physical gate oxide thickness as thin as 1.2nm have been demonstrated. Significant pFET enhancement has been achieved.