This paper presents a GSM / GPRS / EDGE polar loop transmitter that utilizes two feedback loops from the output of the power amplifier (PA), one for the amplitude and the other for the phase of the transmitted signal. This architecture has the advantage of using a high efficiency nonlinear PA since AM-AM distortion is compensated by the amplitude loop. It is also insensitive to AM-PM distortion from the PA since it is compensated by the phase feedback loop. The input signal to the PA is phase modulated with constant amplitude. The amplitude modulation is added at the output by varying the gain of the PA. The dual feedback loops ensure robust performance under component and load variations. The transmitter maintains excellent EVM under VSWR without the need for an isolator. There is no need for pre-or post-PA filtering to meet the receive band noise requirement. The losses of the isolator and SAW filter are avoided, which translates into higher overall system efficiency. The required dynamic range of 55dB is easily achieved under closed-loop power control. Figure 10.3.1 shows a simplified block diagram of the polar loop transmitter (several patents pending). Unlike previous approaches [1], the presented architecture has feedback control on both phase and amplitude. The phase and amplitude loops share a common path that includes a coupler, a down-converting mixer, and an IF variable gain amplifier (VGA). At this point the two loops separate. The phase loop is based on a translational loop with the IQ Modulator in its feedback path [2]. The UHF VCO, locked to a crystal oscillator by the fractional-N synthesizer (not shown) is divided down by M and M*N to create the LO1 signal and the reference IF signal, IFref. LO1 is used to down convert the portion of the PA output applied to the mixer via the coupler, RFf. The IF signal is amplified in the IFVGA. The amplitude variation of the feedback signal is removed in Limiter1, and the resulting signal is used as the up-converting LO2 for the IQ modulator. This signal is then modulated by the I and Q base-band signals. The output of the IQ modulator, IFm, has both amplitude and phase variation. The amplitude variation of IFm is removed by Limiter2, and the resulting signal is fed to the phase-frequency detector (PFD). The PFD extracts the phase error between the reference signal IFref and the feedback signal IFml. The charge pump (CP) and loop filter convert the phase error into a voltage, and close the phase loop by adjusting the control voltage of RF VCO. The output of the RF VCO is buffered and applied to the RF input of the PA.The output of the IQ modulator, IFm, is also applied to a bandpass filter, BPF2, which is then buffered, and the resulting signal's envelope is extracted in detector D1. This envelope, Aref, serves as the reference for the amplitude loop. The envelope of the IFVGA output is extracted in detector D2 creating the feedback amplitude, Af. The feedback envelope is subtracted from the reference envelope, and the error signal is amplified by the base-band...
There has been an increased demand for 3G cell phones that support multiple bands of operation and are backward compatible with the 2G/2.5G standard to provide coverage where 3G networks have not yet been fully deployed. The transceiver design for such a handset becomes complicated with the need for separate transceivers for 3G and 2G/2.5G [1,2] or for multiple inter-stage receive / transmit SAW filters [3]. A single-chip transceiver that operates as a multimode multiband radio and eliminates the inter-stage receive / transmit SAW filters is presented. Figure 6.3.1 shows the block diagram of the transceiver with 7 primary and 4 diversity bands in WCDMA, and quad band in GSM. The transceiver is designed to operate in any of the UTRA bands 1 to 10, with the exception of band 7. It supports HSDPA (Cat 1-12), HSUPA (Cat 1-6), EGPRS (Classes 1-12, 30-39), and compressed mode of EGPRS / WCDMA operation. The transceiver is compliant with 3G DigRF interface 3.09.The analog / RF section of the transmitter is shown in Fig. 6.3.2. The I/Q DAC is based on oversampled current steering with 10b accuracy realized with a 6b-unary and 4b-binary segmentation. The output of the DAC is fed to a 3 rdorder Chebyshev continuous-time filter that attenuates out-of-band noise and DAC images and drives the I/Q modulator. The filter can be configured to operate in WCDMA, GMSK or EDGE mode. The I/Q modulator is a passive LO-2LO mixer. Two levels of passive switches are driven by LO and 2×LO frequencies with proper phases. This mixer configuration achieves both lower phase noise in the LO path and isolation between I and Q baseband inputs, and addresses the stringent linearity and noise requirements of GSM/WCDMA. The differential output of the I/Q modulator is converted to single-ended output using an on-chip balun. The balun output is then amplified in the driver stage and sent off-chip to the PA. The transmitter provides 80dB of gain-control range in WCDMA mode and 40dB in EDGE mode. The gain control is distributed across the chain and designed to meet the linearity and noise requirements over power-control range, while optimizing the current consumption. At high power (24 to 0dBm) a closed-loop power control scheme in the transceiver is used for accurate power control, and at lower power (0 to -57dBm) a conventional power-control scheme through the base-station is used.The architecture of the receiver front-end is shown in Fig. 6.3.3. The mixers and LO buffers are shared among several LNAs to reduce die area. The mixer outputs are connected to the virtual grounds created by the transimpedance amplifiers (TIAs) and its inputs are driven by the output current from the LNA. In this current-driven passive-mixer topology, the voltage swings at the mixer input and output are significantly reduced, resulting in improved linearity. In a passive mixer design, the noise contribution of the TIA increases as the impedance at the mixer input decreases. Therefore, an LC tank is used at the LNA cascode output with switchable capacitors to adjust the tan...
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